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📄 646xx.h

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EXTERN xdata volatile unsigned char USBPAIR		_AT_	0x7FDD;	// USB Endpoint Pairing
#define ISOSEND0		0x80
#define	PR6OUT			0x20
#define	PR4OUT			0x10
#define	PR2OUT			0x08
#define	PR6IN			0x04
#define	PR4IN			0x02
#define	PR2IN			0x01
EXTERN xdata volatile unsigned char IN07VAL		_AT_	0x7FDE;	// Endpoints 0-7 IN Valid Bits
EXTERN xdata volatile unsigned char OUT07VAL	_AT_	0x7FDF;	// Endpoints 0-7 OUT Valid Bits
EXTERN xdata volatile unsigned char INISOVAL	_AT_	0x7FE0;	// Isochronous IN Endpoint Valid Bits
EXTERN xdata volatile unsigned char OUTISOVAL	_AT_	0x7FE1;	// Isochronous OUT Endpoint Valid Bits

/* Fast Transfers */
EXTERN xdata volatile unsigned char FASTXFR		_AT_	0x7FE2;	// Fast Transfer Control
#define	FISO			0x80
#define	FBLK			0x40
#define	RPOL			0x20
#define	RMOD			0x18
#define	WPOL			0x04
#define	WMOD			0x03
EXTERN xdata volatile unsigned short AUTOPTR	_AT_	0x7FE3;	// Auto Pointer Address
//EXTERN xdata volatile unsigned char AUTOPTRH	_AT_	0x7FE3;	// Auto Pointer Address High
//EXTERN xdata volatile unsigned char AUTOPTRL	_AT_	0x7FE4;	// Auto Pointer Address High
EXTERN xdata volatile unsigned char AUTODATA	_AT_	0x7FE5;	// Auto Pointer Data

/* Setup Data */
EXTERN xdata volatile unsigned char SETUPBUF[8] _AT_	0x7FE8;	// Setup Data Buffer

/* Isochronous FIFO Sizes */
EXTERN xdata volatile unsigned char OUT8ADDR	_AT_	0x7FF0;	// ISO OUT Endpoint 8 Start Address
EXTERN xdata volatile unsigned char OUT9ADDR	_AT_	0x7FF1;	// ISO OUT Endpoint 9 Start Address
EXTERN xdata volatile unsigned char OUT10ADDR	_AT_	0x7FF2;	// ISO OUT Endpoint 10 Start Address
EXTERN xdata volatile unsigned char OUT11ADDR	_AT_	0x7FF3;	// ISO OUT Endpoint 11 Start Address
EXTERN xdata volatile unsigned char OUT12ADDR	_AT_	0x7FF4;	// ISO OUT Endpoint 12 Start Address
EXTERN xdata volatile unsigned char OUT13ADDR	_AT_	0x7FF5;	// ISO OUT Endpoint 13 Start Address
EXTERN xdata volatile unsigned char OUT14ADDR	_AT_	0x7FF6;	// ISO OUT Endpoint 14 Start Address
EXTERN xdata volatile unsigned char OUT15ADDR	_AT_	0x7FF7;	// ISO OUT Endpoint 15 Start Address
EXTERN xdata volatile unsigned char IN8ADDR		_AT_	0x7FF8;	// ISO IN Endpoint 8 Start Address
EXTERN xdata volatile unsigned char IN9ADDR		_AT_	0x7FF9;	// ISO IN Endpoint 9 Start Address
EXTERN xdata volatile unsigned char IN10ADDR	_AT_	0x7FFA;	// ISO IN Endpoint 10 Start Address
EXTERN xdata volatile unsigned char IN11ADDR	_AT_	0x7FFB;	// ISO IN Endpoint 11 Start Address
EXTERN xdata volatile unsigned char IN12ADDR	_AT_	0x7FFC;	// ISO IN Endpoint 12 Start Address
EXTERN xdata volatile unsigned char IN13ADDR	_AT_	0x7FFD;	// ISO IN Endpoint 13 Start Address
EXTERN xdata volatile unsigned char IN14ADDR	_AT_	0x7FFE;	// ISO IN Endpoint 14 Start Address
EXTERN xdata volatile unsigned char IN15ADDR	_AT_	0x7FFF;	// ISO IN Endpoint 15 Start Address


/************** Special Function Registers ***************/

/*	NOTE that the SFRs and the bit positions are described
	in table 17-4 										 */

/* Processor Misc */
sfr SP = 0x81;		// Stack Pointer
sfr PSW = 0xD0;		// Program Status Word
			sbit CY    = 0xD0+7;	// Carry flag
			sbit AC    = 0xD0+6;	// Auxillary carry flag
			sbit F0    = 0xD0+5;	// User flag 0
			sbit RS1   = 0xD0+4;	// Register bank select bit 1
			sbit RS0   = 0xD0+3;	// Register bank select bit 0
			sbit OV    = 0xD0+2;	// Overflow flag
			sbit FL    = 0xD0+1;	// User flag 1
			sbit P     = 0xD0+0;	// Parity flag
sfr ACC = 0xE0;		// Accumulator
sfr B = 0xF0;		// B Register

/* Dual Data Pointers */
sfr DPL0 = 0x82;	// Data Pointer 0 Low Addr
sfr DPH0 = 0x83;	// Data Pointer 0 High Addr
sfr DPL1 = 0x84;	// Data Pointer 1 Low Addr
sfr DPH1 = 0x85;	// Data Pointer 1 High Addr
sfr DPS = 0x86;		// Data Pointer Select
			sbit SEL	= 0x86+0;	//
sfr MPAGE = 0x92;	// Replaces std port 2 for indirect memory addressing

/* Timers */
sfr TCON = 0x88;	// Timer 0 & 1 Control
			sbit TF1    = 0x88+7;	// Timer 1 overflow flag
			sbit TR1    = 0x88+6;	// Timer 1 run control
			sbit TF0    = 0x88+5;	// Timer 0 overflow flag
			sbit TR0    = 0x88+4;	// Timer 0 run control
			sbit IE1    = 0x88+3;	// Interrupt 1 edge detect
			sbit IT1    = 0x88+2;	// Interrupt 1 type select
			sbit IE0    = 0x88+1;	// Interrupt 0 edge detect
			sbit IT0    = 0x88+0;	// Interrupt 0 type select
sfr TMOD = 0x89;	//
			sbit GATE1	= 0x89+7;	// Timer 1 gate control
			sbit C_T1	= 0x89+6;	// Counter/Timer Select
			sbit M11	= 0x89+5;	// Timer 1 mode select bit 1
			sbit M01	= 0x89+4;	// Timer 1 mode select bit 0
			sbit GATE0	= 0x89+3;	// Timer 0 gate control
			sbit C_T0	= 0x89+2;	// Counter/Timer Select
			sbit M10	= 0x89+1;	// Timer 0 mode select bit 1
			sbit M00	= 0x89+0;	// Timer 0 mode select bit 0
sfr TL0 = 0x8A;		// Timer 0 L
sfr TL1 = 0x8B;		// Timer 1 L
sfr TH0 = 0x8C;		// Timer 0 H
sfr TH1 = 0x8D;		// Timer 1 H
sfr CKCON = 0x8E;	// Clock Configuration
			sbit T2M	= 0x8E+5;	// Timer 2 clock select
			sbit T1M	= 0x8E+4;	// Timer 1 clock select
			sbit T0M	= 0x8E+3;	// Timer 0 clock select
			sbit MD2	= 0x8E+2;	// Control the number of cycles for ext MOVX
			sbit MD1	= 0x8E+1;
			sbit MD0	= 0x8E+0;




/* Timer 2 */
sfr T2CON = 0xC8;	// Timer 2 Control
			sbit TF2	= 0xC8+7;	// Timer 2 overflow flag
			sbit EXF2	= 0xC8+6;	// Timer 2 external flag
			sbit RCLK	= 0xC8+5;	// Receive clock flag
			sbit TCLK	= 0xC8+4;	// Transmit clock flag
			sbit EXEN2	= 0xC8+3;	// Timer 2 external enable
			sbit TR2	= 0xC8+2;	// Timer 2 run control flag
			sbit C_T2	= 0xC8+1;	// Counter/Timer select 
			sbit CP_RL2	= 0xC8+0;	// Capture/reload flag
sfr RCAP2L = 0xCA;	// T2 Capture/Reload Value L
sfr RCAP2H = 0xCB;	// T2 Capture/Reload Value H
sfr T2L = 0xCC;		// T2 Count L
sfr T2H = 0xCD;		// T2 Count H
sfr IE = 0xA8;		// ET2-Enable T2 Interrupt Bit
			sbit EA    = 0xA8+7;	// Global interrupt enable
			sbit ES1   = 0xA8+6;	// Enable serial port 1 interrupt
			sbit ET2   = 0xA8+5;	// Enable Timer 2 interrupt
			sbit ES0   = 0xA8+4;	// Enable Serial port 0 interrupt
			sbit ET1   = 0xA8+3;	// Enable Timer 1 interrupt
			sbit EX1   = 0xA8+2;	// Enable external interrupt 1
			sbit ET0   = 0xA8+1;	// Enable Timer 0 interrupt
			sbit EX0   = 0xA8+0;	// Enable external interrupt 0
sfr IP = 0xB8;		// PT2-T2 Interrupt Priority Control
			sbit PS1   = 0xB8+6;	// Serial port 1 interrupt priority control
			sbit PT2   = 0xB8+5;	// Timer 2 interrupt priority control
			sbit PS0   = 0xB8+4;	// Serial port 0 interrupt priority control
			sbit PT1   = 0xB8+3;	// Timer 1 interrrupt priority control
			sbit PX1   = 0xB8+2;	// External interrupt 1 priority control
			sbit PT0   = 0xB8+1;	// Timer 0 interrupt priority control
			sbit PX0   = 0xB8+0;	// External interrupt 0 priority control

/* Serial Ports */
sfr SCON0 = 0x98;	// Serial Port 0 Control
			sbit SM0_0	= 0x98+7;	// Serial Port 0 mode bit 0
			sbit SM1_0	= 0x98+6;	// Serial port 0 mode bit 1
			sbit SM2_0	= 0x98+5;	// Multiprocessor communications enable
			sbit REN_0	= 0x98+4;	// Receive enable
			sbit TB8_0	= 0x98+3;	// Defines the statof the 9th data bit transmitted in modes 2 and 3
			sbit RB8_0	= 0x98+2;	// In modes 2 and 3, indicates state of 9th bit
			sbit TI_0	= 0x98+1;	// Transmit interrupt flag
			sbit RI_0	= 0x98+0;	// Receive interrupt flag
sfr SBUF0 = 0x99;	// Serial Port 0 Buffer

/* UART1 */
sfr SCON1 = 0xC0;	// Serial Port 1 Control
			sbit SM0_1  = 0xC0+7;	// Serial Port 1 mode bit 0
			sbit SM1_1  = 0xC0+6;	// Serial Port 1 mode bit 1
			sbit SM2_1  = 0xC0+5;	// Multiprocessor communications enable
			sbit REN_1  = 0xC0+4;	// Receive enable
			sbit TB8_1  = 0xC0+3;	// Defines the statof the 9th data bit transmitted in modes 2 and 3
			sbit RB8_1  = 0xC0+2;	// In modes 2 and 3, indicates state of 9th bit
			sbit TI_1   = 0xC0+1;	// Transmit interrupt flag
			sbit RI_1   = 0xC0+0;	// Receive interrupt flag
sfr SBUF1 = 0xC1;	// Serial Port 1 Data
//sfr IE6 = 0xA8;		// ES1-SiO1 Interrupt Enable Bit
//sfr IP6 = 0xB8;		// PS1-SIO1 Interrupt Priority Control
sfr EICON = 0xD8;	// SMOD1-SIO1 Baud Rate Doubler
			sbit SMOD1 = 0xD8+7;	// Serial port 1 baud rate doubler control
			sbit ERESI = 0xD8+5;	// Enable resume interrupt
			sbit RESI  = 0xD8+4;	// Wakeup interrupt flag
			sbit INT6EN  = 0xD8+3;	// External interrupt 6

/* Interrupts - see 18.3.8 for definitions */
sfr EXIF = 0x91;	// INT2-INT5 Interrupt Flags
			sbit IE5	= 0x91+7;	// External interrupt 5 flag
			sbit IE4	= 0x91+6;	// External interrupt 4 flag
			sbit I2CINT	= 0x91+5;	// External interrupt 3 flag
			sbit USBINT	= 0x91+4;	// External interrupt 2 flag
sfr EIE = 0xE8;		// INT2-INT5 Interupt Enables
			sbit EIEX6   = 0xE8+4;	// Enable external interrupt 6
			sbit EIEX5   = 0xE8+3;	// Enable external interrupt 5
			sbit EIEX4   = 0xE8+2;	// Enable external interrupt 4
			sbit EI2C    = 0xE8+1;	// Enable external interrupt 3
			sbit EUSB    = 0xE8+0;	// Enable USB interrupt
sfr EIP = 0xF8;		// INT2-INT5 Interrupt Priority Control
			sbit EIPX6   = 0xF8+4;	// External interrupt 6 priority control
			sbit EIPX5   = 0xF8+3;	// External interrupt 5 priority control
			sbit EIPX4   = 0xF8+2;	// External interrupt 4 priority control
			sbit PI2C    = 0xF8+1;	// External interrupt 3 priority control
			sbit PUSB    = 0xF8+0;	// External interrupt 2 priority control
//sfr EICON = 0xD8;	// INT6 Interrupt Flag
//sfr EIE = 0xE8;		// INT6 Interrupt Enable
//sfr EIP = 0xF8;		// INT6 Interrupt Priority Control
//sfr EICON = 0xD8;	// WAKEUP# Interrupt Flag
//sfr EICON = 0xD8;	// WAKEUP# Interrupt Enable 

/* Expanded SFRs */
sfr	IOA	= 0x80;		// Input/Output A		
sfr	IOB	= 0x90;		// Input/Output B
sfr	IOC	= 0xA0;		// Input/Output C
sfr	IOD	= 0xB0;		// Input/Output D
sfr	IOE	= 0xB1;		// Input/Output E
sfr INT2CLR = 0xA1;	// Interrupt 2 Clear
sfr INT4CLR = 0xA2;	// Interrupt 4 Clear
//sfr	OEA = 0xB2;		// Output Enable A 
//sfr	OEB = 0xB3;		// Output Enable B
//sfr	OEC = 0xB4;		// Output Enable C
//sfr	OED = 0xB5;		// Output Enable D
//sfr	OEE = 0xB6;		// Output Enable E

/* Idle Mode */
sfr PCON = 0x87;	// EZ-USB FX Power Down (Suspend)
			sbit SMOD0	= 0x87+7;	//
			sbit GF1	= 0x87+3;	//
			sbit GF0	= 0x87+2;	//
			sbit STOP	= 0x87+1;	// 
			sbit IDLE	= 0x87+0;	//



/************** interrupt vector numbers *****************/

/* NOTE that this table in defined in Chp 12 */

#define	INT0_VECT	0	// INT0# Pin
#define	TMR0_VECT	1	// Timer 0 Overflow
#define	INT1_VECT	2	// INT1# Pin
#define	TMR1_VECT	3	// Timer 1 Overflow
#define	COM0_VECT	4	// UART0 Rx & Tx
#define	TMR2_VECT	5	// Timer 2 Overflow
#define	WKUP_VECT	6	// WAKEUP# Pin or USB Core
#define	COM1_VECT	7	// UART1 Rx & Tx
#define	USB_VECT	8	// USB Core (INT2)
#define	I2C_VECT	9	// I2C (INT3)
#define	INT4_VECT	10	// Slave FIFOs/INT4 pin
#define	INT5_VECT	11	// INT5# Pin
#define	INT6_VECT	12	// INT6 Pin

#endif

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