📄 lpc_vector_init.s
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/*
***********************************************************************
Embest Info&Tech Co., Ltd. All rights reserved.
www.embedinfo.com
***********************************************************************
---------------- file information -------------------------------------
file name: lpc_vector_init.s
version : v0
author : peter pan / panqan@hotmail.com
panqian@embedinfo.com
begin : 2006-02-10
finish : 2006-02-10
define : lpc** vector input source define
notes :
---------------- modify information -----------------------------------
version :
modify :
begin :
finish :
define :
-----------------------------------------------------------------------
*/
.INCLUDE "..\\..\\com\\init_lpc\\lpc_vector_init_condition.inc"
#need for init lpc about hardware register
#(-----------------------------------------------------------------
.EQU MEMMAP, 0xE01FC040
.EQU VICIntEnClr, 0xFFFFF030
.EQU BCFG0, 0xFFE00000
.EQU BCFG1, 0xFFE00004
.EQU PINSEL2, 0xe002c014
#-----------------------------------------------------------------)
#arm mode define used for change the work mode to cpsr
#(-----------------------------------------------------------------
# 7 work mode
.EQU Mode_USR, 0x10
.EQU Mode_FIQ, 0x11
.EQU Mode_IRQ, 0x12
.EQU Mode_SVC, 0x13
.EQU Mode_ABT, 0x17
.EQU Mode_UND, 0x1B
.EQU Mode_SYS, 0x1F
# interrupt shield bit
.EQU I_Bit, 0x80
.EQU F_Bit, 0x40
# state define bit
.EQU T_bit, 0x20
#-----------------------------------------------------------------)
#vectors
#needless change
#(---------------------------------------------vectors map---------
.globl _start
.code 32
.TEXT
_start:
LDR PC, Reset_Addr
LDR PC, Undef_Addr
LDR PC, SWI_Addr
LDR PC, PAbt_Addr
LDR PC, DAbt_Addr
.long 0xb9205f80
@ keep interrupt vectors sum is 0
LDR PC, [PC, #-0xff0]
LDR PC, FIQ_Addr
Reset_Addr: .long Reset_Handler
Undef_Addr: .long Undef_Handler
SWI_Addr: .long SWI_Handler
PAbt_Addr: .long PAbt_Handler
DAbt_Addr: .long DAbt_Handler
.long 0
IRQ_Addr: .long IRQ_Handler
FIQ_Addr: .long FIQ_Handler
#----------------------------------------------vectors map--------)
#normal operation needless Handler
#perhaps you can change or add your codes
#(---------------------------------------------needless vectors----
Undef_Handler:
B Undef_Handler
PAbt_Handler:
B PAbt_Handler
DAbt_Handler:
B DAbt_Handler
#----------------------------------------------needless vectors---)
Reset_Handler: @The reset handler
#(---------------------------------------------delay 1s------------
#wait the targer input a stabilization state,do this delay, if in
#quick need system,it can be cancel,but it can make the system more
#strong.
ldr r0, =0x0f
strong_delay:
subs r0, r0, #1
bne strong_delay
#----------------------------------------------delay 1s-----------)
LDR R0, =PINSEL2
LDR R1, =0x0FF169D4
STR R1, [R0]
LDR R0, =BCFG0
LDR R1, =0x10000023
LDR R1, =0x10001842
STR R1, [R0]
LDR R0, =BCFG1
LDR R1, =0x10000821
STR R1, [R0]
# Setup the stack for each mode
#(---------------------------------------------init stack ---------
InitStack:
# MOV R1, LR
LDR R0, =Top_Stack
# UND stack sp
MSR CPSR_c, #(Mode_UND|I_Bit|F_Bit)
MOV SP, R0
SUB R0, R0, #(UND_Stack_Size)
# ABT stack sp
MSR CPSR_c, #(Mode_ABT|I_Bit|F_Bit)
MOV SP, R0
SUB R0, R0, #(ABT_Stack_Size)
# FIQ stack sp
MSR CPSR_c, #(Mode_FIQ|I_Bit|F_Bit)
MOV SP, R0
SUB R0, R0, #(FIQ_Stack_Size)
# UND IRQ sp
MSR CPSR_c, #(Mode_IRQ|I_Bit|F_Bit)
MOV SP, R0
SUB R0, R0, #(IRQ_Stack_Size)
# UND SVC sp
MSR CPSR_c, #(Mode_SVC|I_Bit|F_Bit)
MOV SP, R0
SUB R0, R0, #(SVC_Stack_Size)
# UND USR sp
MSR CPSR_c, #(Mode_USR|I_Bit|F_Bit)
MOV SP, R0
# MOV PC, R1
#----------------------------------------------init stack ---------)
#only for blamed GCC compiler, you'd better check your compiler
#(---------------------------------------------for Gcc need--------------------------
#------------------------------------------------------------------------------
#- Initialise C variables
#------------------------
#- Following labels are automatically generated by the linker.
#- RO: Read-only = the code
#- RW: Read Write = the data pre-initialized and zero-initialized.
#- ZI: Zero-Initialized.
#- Pre-initialization values are located after the code area in the image.
#- Zero-initialized datas are mapped after the pre-initialized.
#- Note on the Data position :
#- If using the ARMSDT, when no -rw-base option is used for the linker, the
#- data area is mapped after the code. You can map the data either in internal
#- SRAM ( -rw-base=0x40 or 0x34) or in external SRAM ( -rw-base=0x2000000 ).
#- Note also that to improve the code density, the pre_initialized data must
#- be limited to a minimum.
#------------------------------------------------------------------------------
.extern Image_RO_Limit /* End of ROM code (=start of ROM data) */
.extern Image_RW_Base /* Base of RAM to initialise */
.extern Image_ZI_Base /* Base and limit of area */
.extern Image_ZI_Limit /* to zero initialise */
ldr r0, =Image_RO_Limit /* Get pointer to ROM data */
ldr r1, =Image_RW_Base /* and RAM copy */
ldr r3, =Image_ZI_Base /* Zero init base => top of initialised data */
cmp r0, r1 /* Check that they are different */
beq NoRW
LoopRw:
cmp r1, r3 /* Copy init data */
ldrcc r2, [r0], #4
strcc r2, [r1], #4
bcc LoopRw
NoRW:
ldr r1, =Image_ZI_Limit /* Top of zero init segment */
mov r2, #0
LoopZI:
cmp r3, r1 /* Zero init */
strcc r2, [r3], #4
bcc LoopZI
#----------------------------------------------for Gcc need-------------------------)
#now let's goto c world, 不再受那汇编苦!!!!!!!!!!!!!!!!!!!
#now let's goto c world, 不再受那汇编苦!!!!!!!!!!!!!!!!!!!
#(---------------------------------------------goto c world--------
.extern Main
#Main:
B Main
#----------------------------------------------goto c world-------)
IRQ_Handler:
B IRQ_Handler
SWI_Handler:
B SWI_Handler
FIQ_Handler:
B FIQ_Handler
.END
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