pci_arbiter.vhd

PCI Arbitor by VHDL

-------------------------------------------------------------------------------
-- Author: Antonio Di Rocco
--         SW Defined Radio Labs
--         SELEX COMMUNICATIONS 
--         A Finmeccanica Company
-------------------------------------------------------------------------------
--    Description: PCI arbiter (for 6 deviices) for PCI bus. 
--                   - All devices may be initiator. 
--                   - Priority management in pure rotation arbitration
--                   - Bus parking (configurable)
--                                              
---------------------------------------------------------------------------
-- Compiler Directives
---------------------------------------------------------------------------

-- library --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;


---------------------------------------------------------------------------
-- Main Module
---------------------------------------------------------------------------

entity PCI_ARBITER is

   generic ( MASTERS   : integer := 6 );
   
   port    (                                                                  ------------------ System signals --------------------
            REQ_N          : in std_logic_vector(MASTERS-1 downto 0);         -- BUS REQUEST signals
            PCI_CLK        : in std_logic ;                                  -- PCI 33MHz Clock          
            PCI_RST        : in std_logic;                                    -- PCI reset                                                               
            FRAME_N        : in std_logic;                                    -- Selected wired or
            IRDY_N         : in std_logic;                                    -- Selected wired or
            
            GNT_N          : out std_logic_vector(MASTERS-1 downto 0)        -- BUS GRANT signals               
            ) ;

end PCI_ARBITER ;

---------------------------------------------------------------------------
-- Main Architecture
---------------------------------------------------------------------------

architecture RTL of PCI_ARBITER is

-- type declarations
type STATE_TYPE is (IDLE,GRANTED,CONTENT);

-- signal declarations

signal STATE,NEXT_STATE  : STATE_TYPE;
signal SYS_CLK           : std_logic;
signal RESET             : std_logic;
signal CNT_DELAY_16      : std_logic_vector(4 downto 0);
signal CTRL              : std_logic_vector(2 downto 0);
signal count_rst         : std_logic;
signal IRDY_N_risedge_FF : std_logic_vector(1 downto 0);
signal REQ_N_FF          : std_logic_vector(MASTERS-1 downto 0);

signal REQ_N_FF_FREZED   : std_logic_vector(MASTERS-1 downto 0);
signal REQ_MASK_0        : std_logic_vector(MASTERS-1 downto 0);
signal REQ_MASK_1        : std_logic_vector(MASTERS-1 downto 0);
signal REQ_MASK_2        : std_logic_vector(MASTERS-1 downto 0);
signal REQ_MASK_3        : std_logic_vector(MASTERS-1 downto 0);
signal REQ_MASK_4        : std_logic_vector(MASTERS-1 downto 0);
signal REQ_MASK_5        : std_logic_vector(MASTERS-1 downto 0);
signal SHIFT_PRIOR       : std_logic_vector(MASTERS-1 downto 0);
signal SHIFT_PRIOR_ena   : std_logic;
signal IRDY_N_risedge    : std_logic;

CONSTANT Bus_parker 		   : std_logic_vector(MASTERS-1 downto 0) := "111110" ;

begin

SYS_CLK  <= PCI_CLK;
RESET    <= PCI_RST;


REQ_N_resampling_P : process (SYS_CLK, RESET)
      begin
         if (RESET = '1') then 
            REQ_N_FF <= (others => '1');
         elsif (SYS_CLK'event and SYS_CLK = '1') then
            REQ_N_FF <= REQ_N;
         end if;
      end process REQ_N_resampling_P;
--------------------------------------------------------

IRDY_N_risedge_P : process (SYS_CLK, RESET)
      begin
         if (RESET = '1') then 
            IRDY_N_risedge_FF <= (others => '1');
         elsif (SYS_CLK'event and SYS_CLK = '1') then
            IRDY_N_risedge_FF <= IRDY_N_risedge_FF(0) & IRDY_N;
         end if;
      end process IRDY_N_risedge_P;
IRDY_N_risedge  <= IRDY_N_risedge_FF(0) AND (not(IRDY_N_risedge_FF(1)));

--------------------------------------------------------

            REQ_MASK_0 <= REQ_N_FF OR  SHIFT_PRIOR;                                
            REQ_MASK_1 <= REQ_N_FF OR (SHIFT_PRIOR(4 DOWNTO 0) & SHIFT_PRIOR(5));
            REQ_MASK_2 <= REQ_N_FF OR (SHIFT_PRIOR(3 DOWNTO 0) & SHIFT_PRIOR(5 DOWNTO 4));
            REQ_MASK_3 <= REQ_N_FF OR (SHIFT_PRIOR(2 DOWNTO 0) & SHIFT_PRIOR(5 DOWNTO 3));
            REQ_MASK_4 <= REQ_N_FF OR (SHIFT_PRIOR(1 DOWNTO 0) & SHIFT_PRIOR(5 DOWNTO 2));
            REQ_MASK_5 <= REQ_N_FF OR (SHIFT_PRIOR(0) & SHIFT_PRIOR(5 DOWNTO 1));

---------------------------------------------------------
 -- state register update process -----------------------
      NEW_STATE_UPDATE_P: process (STATE,REQ_N_FF,IRDY_N_risedge,CNT_DELAY_16,SHIFT_PRIOR,REQ_MASK_0,REQ_MASK_1,REQ_MASK_2,REQ_MASK_3,REQ_MASK_4,REQ_MASK_5)
      begin
         --  generated signals : SHIFT_PRIOR_ena  count_rst NEXT_STATE REQ_N_FF_FREZED
            
            case STATE is
              when IDLE =>                                  
               if ( REQ_N_FF  = "111111" ) then                    -- no bus request 
                  NEXT_STATE <= IDLE;
                  count_rst <= '1'; 
                  SHIFT_PRIOR_ena <= '0';
                  --REQ_N_FF_FREZED <= "111110";                     -- bus parking on Device 0 -
               elsif ( (REQ_N_FF = "111110") OR (REQ_N_FF = "111101") OR (REQ_N_FF = "111011") OR (REQ_N_FF = "110111") OR (REQ_N_FF = "101111") OR (REQ_N_FF = "011111") ) then
                  NEXT_STATE <= GRANTED;                          -- one bus request
                  count_rst <= '1'; 
                  REQ_N_FF_FREZED <= REQ_N_FF;
                  SHIFT_PRIOR_ena <= '1';       --SHIFT_PRIOR --deve shiftare + 1;              -- increment priority - lo faccio solo nel passaggio si stato  e mai pi