pwm.vhd

一个在CPLD

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY pwm IS
	PORT
	(
		clk		: IN	STD_LOGIC;
		key		: IN	STD_LOGIC_VECTOR(1 DOWNTO 0);
		diode	: OUT   STD_LOGIC_vector(4 downto 0);
		led		: out	std_logic_vector(7 downto 0);
		cs		: out	std_logic_vector(3 downto 0);
		pwm_out : OUT	STD_LOGIC
	);
END pwm;
ARCHITECTURE a OF pwm IS

SIGNAL q : STD_LOGIC_vector(15 downto 0);
SIGNAL pwm_cnt : STD_LOGIC_vector(4 downto 0);
SIGNAL pwm_buf : STD_LOGIC;
SIGNAL cnt_change : STD_LOGIC;
	
BEGIN
	led <= "11111111";
	diode <= "11111";
	cs <= "1111";
	process(clk)
	begin
	if(clk'event and clk = '1') then 
		q <= q+1;
		if (q(13 downto 9) < pwm_cnt)then
			pwm_buf <= '1';
		else
			pwm_buf <= '0';
		end if;
		if (q(14)='1') then
			if cnt_change = '0' then
				cnt_change <= '1';
				if (key(0) = '1') then
					pwm_cnt <= pwm_cnt+2;
				elsif (key(1) = '1')then
					pwm_cnt <= pwm_cnt-2;
				end if;
			end if;
		else
			cnt_change <= '0';
		end if;
	end if;
	end process;
	pwm_out <= pwm_buf;

END a;