pwm.v

来自「一个在CPLD」· Verilog 代码 · 共 44 行

module pwm(clock,keyin,pwm_out);
    input clock;
    input [1:0] keyin;
    output pwm_out;

	reg [20:0] count;
 	reg [9:0] pwm_count;
	reg cnt_chg;
	reg pwm_reg;

always @(posedge clock)
begin
	count=count+1;
	if (count[13:4] < pwm_count)
		pwm_reg=1;
	else
		pwm_reg=0;


	if (count[15] == 1'b1)
	begin
		if (cnt_chg == 1'b1)
		begin
			cnt_chg = 1'b0;
			if (keyin[0] == 1'b0)
			begin
					pwm_count=pwm_count+1;
			end
			else if (keyin[1] == 1'b0)
			begin
					pwm_count=pwm_count-1;
			end
		end
	end
	else
		cnt_chg = 1'b1;

end

assign pwm_out=pwm_reg;

endmodule