pwm.tan.rpt

一个在CPLD

+--------------------------------------------------------------------------+
; th                                                                       ;
+---------------+-------------+-----------+--------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To         ; To Clock ;
+---------------+-------------+-----------+--------+------------+----------+
; N/A           ; None        ; -3.000 ns ; key[0] ; pwm_cnt[1] ; clk      ;
; N/A           ; None        ; -3.000 ns ; key[0] ; pwm_cnt[2] ; clk      ;
; N/A           ; None        ; -3.000 ns ; key[0] ; pwm_cnt[3] ; clk      ;
; N/A           ; None        ; -3.000 ns ; key[0] ; pwm_cnt[4] ; clk      ;
; N/A           ; None        ; -3.000 ns ; key[1] ; pwm_cnt[1] ; clk      ;
; N/A           ; None        ; -3.000 ns ; key[1] ; pwm_cnt[2] ; clk      ;
; N/A           ; None        ; -3.000 ns ; key[1] ; pwm_cnt[3] ; clk      ;
; N/A           ; None        ; -3.000 ns ; key[1] ; pwm_cnt[4] ; clk      ;
+---------------+-------------+-----------+--------+------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Apr 07 20:52:45 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off PWM -c pwm
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 47.62 MHz between source register "lpm_counter:q_rtl_0|dffs[11]" and destination register "pwm_buf" (period= 21.0 ns)
    Info: + Longest register to register delay is 16.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC121; Fanout = 6; REG Node = 'lpm_counter:q_rtl_0|dffs[11]'
        Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 10.000 ns; Loc. = SEXP115; Fanout = 1; COMB Node = 'LessThan~413'
        Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 16.000 ns; Loc. = LC128; Fanout = 1; REG Node = 'pwm_buf'
        Info: Total cell delay = 14.000 ns ( 87.50 % )
        Info: Total interconnect delay = 2.000 ns ( 12.50 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 21; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC128; Fanout = 1; REG Node = 'pwm_buf'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 21; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC121; Fanout = 6; REG Node = 'lpm_counter:q_rtl_0|dffs[11]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register "pwm_cnt[1]" (data pin = "key[0]", clock pin = "clk") is 11.000 ns
    Info: + Longest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_33; Fanout = 7; PIN Node = 'key[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC7; Fanout = 8; REG Node = 'pwm_cnt[1]'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
    Info: + Micro setup delay of destination is 4.000 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 21; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC7; Fanout = 8; REG Node = 'pwm_cnt[1]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "pwm_out" through register "pwm_buf" is 8.000 ns
    Info: + Longest clock path from clock "clk" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 21; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC128; Fanout = 1; REG Node = 'pwm_buf'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC128; Fanout = 1; REG Node = 'pwm_buf'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_81; Fanout = 0; PIN Node = 'pwm_out'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: th for register "pwm_cnt[1]" (data pin = "key[0]", clock pin = "clk") is -3.000 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 21; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC7; Fanout = 8; REG Node = 'pwm_cnt[1]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 4.000 ns
    Info: - Shortest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_33; Fanout = 7; PIN Node = 'key[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC7; Fanout = 8; REG Node = 'pwm_cnt[1]'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Apr 07 20:52:46 2006
    Info: Elapsed time: 00:00:02