registerfile.v

若干VHDL语言的源代码

		Registers15=`Def_PCInitValue;
		
		Registers8_FIQ =`WordZero;
		Registers9_FIQ =`WordZero;
		Registers10_FIQ =`WordZero;
		Registers11_FIQ =`WordZero;
		Registers12_FIQ =`WordZero;
		Registers13_FIQ =`WordZero;
		Registers14_FIQ =`WordZero;
		Registers13_SVC =`WordZero;
		Registers14_SVC =`WordZero;
		Registers13_ABT =`WordZero;
		Registers14_ABT =`WordZero;
		Registers13_IRQ =`WordZero;
		Registers14_IRQ =`WordZero;
		Registers13_UND =`WordZero;
		Registers14_UND =`WordZero;
		
		LocalForwardRegister=`WordZero;
	end
	else
	begin
		if(in_WriteEnable==1'b1)
		begin
		   case (in_WriteRegisterNumber)
			8'b0000_0000:
				Registers0=in_WriteBus;
			8'b0000_0001:
				Registers1=in_WriteBus;
			8'b0000_0010:
				Registers2=in_WriteBus;
			8'b0000_0011:
				Registers3=in_WriteBus;
			8'b0000_0100:
				Registers4=in_WriteBus;
			8'b0000_0101:
				Registers5=in_WriteBus;
			8'b0000_0110:
				Registers6=in_WriteBus;
			8'b0000_0111:
				Registers7=in_WriteBus;
			8'b0000_1000:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
				begin
					Registers8=in_WriteBus;
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers8_FIQ=in_WriteBus;
				else
					Registers8=in_WriteBus;
			end
			8'b0000_1001:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
				begin
					Registers9=in_WriteBus;
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers9_FIQ=in_WriteBus;
				else
					Registers9=in_WriteBus;
			end
			8'b0000_1010:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
				begin
					Registers10=in_WriteBus;
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers10_FIQ=in_WriteBus;
				else
					Registers10=in_WriteBus;
			end
			8'b0000_1011:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
				begin
					Registers11=in_WriteBus;
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers11_FIQ=in_WriteBus;
				else
					Registers11=in_WriteBus;
			end
			8'b0000_1100:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
				begin
					Registers12=in_WriteBus;
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers12_FIQ=in_WriteBus;
				else
					Registers12=in_WriteBus;
			end
			8'b0000_1101:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
				begin
					Registers13=in_WriteBus;
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers13_FIQ=in_WriteBus;
				else if(in_ProcessorMode==`MODE_SVC)
					Registers13_SVC=in_WriteBus;
				else if(in_ProcessorMode==`MODE_ABT)
					Registers13_ABT=in_WriteBus;
				else if(in_ProcessorMode==`MODE_IRQ)
					Registers13_IRQ=in_WriteBus;
				else if(in_ProcessorMode==`MODE_UND)
					Registers13_UND=in_WriteBus;
				else
					Registers13=in_WriteBus;
			end
			8'b0000_1110:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
					Registers14=in_WriteBus;
				if(in_IfChangeState==1'b1)
				begin
					case(in_ChangeStateAction)
					`MODE_FIQ:
						Registers14_FIQ=in_WriteBus;
					`MODE_SVC:
						Registers14_SVC=in_WriteBus;
					`MODE_ABT:
						Registers14_ABT=in_WriteBus;
					`MODE_IRQ:
						Registers14_IRQ=in_WriteBus;
					`MODE_UND:
						Registers14_UND=in_WriteBus;
					default:
						Registers14=in_WriteBus;
					endcase
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers14_FIQ=in_WriteBus;
				else if(in_ProcessorMode==`MODE_SVC)
					Registers14_SVC=in_WriteBus;
				else if(in_ProcessorMode==`MODE_ABT)
					Registers14_ABT=in_WriteBus;
				else if(in_ProcessorMode==`MODE_IRQ)
					Registers14_IRQ=in_WriteBus;
				else if(in_ProcessorMode==`MODE_UND)
					Registers14_UND=in_WriteBus;
				else
					Registers14=in_WriteBus;
			end
			8'b0000_1111:
				Registers15=in_WriteBus;
			`Def_LocalForwardRegister:
				LocalForwardRegister=in_WriteBus;
		   endcase
		end


		//the second write port is reserve for pc update
		if(in_SecondWriteEnable==1'b1)
		begin
		   case (in_SecondWriteRegisterNumber)
			8'b0000_0000:
				Registers0=in_SecondWriteBus;
			8'b0000_0001:
				Registers1=in_SecondWriteBus;
			8'b0000_0010:
				Registers2=in_SecondWriteBus;
			8'b0000_0011:
				Registers3=in_SecondWriteBus;
			8'b0000_0100:
				Registers4=in_SecondWriteBus;
			8'b0000_0101:
				Registers5=in_SecondWriteBus;
			8'b0000_0110:
				Registers6=in_SecondWriteBus;
			8'b0000_0111:
				Registers7=in_SecondWriteBus;
			8'b0000_1000:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
				begin
					Registers8=in_SecondWriteBus;
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers8_FIQ=in_SecondWriteBus;
				else
					Registers8=in_SecondWriteBus;
			end
			8'b0000_1001:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
				begin
					Registers9=in_SecondWriteBus;
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers9_FIQ=in_SecondWriteBus;
				else
					Registers9=in_SecondWriteBus;
			end
			8'b0000_1010:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
				begin
					Registers10=in_SecondWriteBus;
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers10_FIQ=in_SecondWriteBus;
				else
					Registers10=in_SecondWriteBus;
			end
			8'b0000_1011:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
				begin
					Registers11=in_SecondWriteBus;
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers11_FIQ=in_SecondWriteBus;
				else
					Registers11=in_SecondWriteBus;
			end
			8'b0000_1100:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
				begin
					Registers12=in_SecondWriteBus;
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers12_FIQ=in_SecondWriteBus;
				else
					Registers12=in_SecondWriteBus;
			end
			8'b0000_1101:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
				begin
					Registers13=in_SecondWriteBus;
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers13_FIQ=in_SecondWriteBus;
				else if(in_ProcessorMode==`MODE_SVC)
					Registers13_SVC=in_SecondWriteBus;
				else if(in_ProcessorMode==`MODE_ABT)
					Registers13_ABT=in_SecondWriteBus;
				else if(in_ProcessorMode==`MODE_IRQ)
					Registers13_IRQ=in_SecondWriteBus;
				else if(in_ProcessorMode==`MODE_UND)
					Registers13_UND=in_SecondWriteBus;
				else
					Registers13=in_SecondWriteBus;
			end
			8'b0000_1110:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
					Registers14=in_SecondWriteBus;
				if(in_IfChangeState==1'b1)
				begin
					case(in_ChangeStateAction)
					`MODE_FIQ:
						Registers14_FIQ=in_SecondWriteBus;
					`MODE_SVC:
						Registers14_SVC=in_SecondWriteBus;
					`MODE_ABT:
						Registers14_ABT=in_SecondWriteBus;
					`MODE_IRQ:
						Registers14_IRQ=in_SecondWriteBus;
					`MODE_UND:
						Registers14_UND=in_SecondWriteBus;
					default:
						Registers14=in_SecondWriteBus;
					endcase
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers14_FIQ=in_SecondWriteBus;
				else if(in_ProcessorMode==`MODE_SVC)
					Registers14_SVC=in_SecondWriteBus;
				else if(in_ProcessorMode==`MODE_ABT)
					Registers14_ABT=in_SecondWriteBus;
				else if(in_ProcessorMode==`MODE_IRQ)
					Registers14_IRQ=in_SecondWriteBus;
				else if(in_ProcessorMode==`MODE_UND)
					Registers14_UND=in_SecondWriteBus;
				else
					Registers14=in_SecondWriteBus;
			end
			8'b0000_1111:
				Registers15=in_SecondWriteBus;
			`Def_LocalForwardRegister:
				LocalForwardRegister=in_SecondWriteBus;
		   endcase
		end

		//the Third write port is reserve for pc update
		if(in_ThirdWriteEnable==1'b1)
		begin
		   case (in_ThirdWriteRegisterNumber)
			8'b0000_0000:
				Registers0=in_ThirdWriteBus;
			8'b0000_0001:
				Registers1=in_ThirdWriteBus;
			8'b0000_0010:
				Registers2=in_ThirdWriteBus;
			8'b0000_0011:
				Registers3=in_ThirdWriteBus;
			8'b0000_0100:
				Registers4=in_ThirdWriteBus;
			8'b0000_0101:
				Registers5=in_ThirdWriteBus;
			8'b0000_0110:
				Registers6=in_ThirdWriteBus;
			8'b0000_0111:
				Registers7=in_ThirdWriteBus;
			8'b0000_1000:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
				begin
					Registers8=in_ThirdWriteBus;
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers8_FIQ=in_ThirdWriteBus;
				else
					Registers8=in_ThirdWriteBus;
			end
			8'b0000_1001:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
				begin
					Registers9=in_ThirdWriteBus;
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers9_FIQ=in_ThirdWriteBus;
				else
					Registers9=in_ThirdWriteBus;
			end
			8'b0000_1010:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
				begin
					Registers10=in_ThirdWriteBus;
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers10_FIQ=in_ThirdWriteBus;
				else
					Registers10=in_ThirdWriteBus;
			end
			8'b0000_1011:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
				begin
					Registers11=in_ThirdWriteBus;
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers11_FIQ=in_ThirdWriteBus;
				else
					Registers11=in_ThirdWriteBus;
			end
			8'b0000_1100:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
				begin
					Registers12=in_ThirdWriteBus;
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers12_FIQ=in_ThirdWriteBus;
				else
					Registers12=in_ThirdWriteBus;
			end
			8'b0000_1101:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
				begin
					Registers13=in_ThirdWriteBus;
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers13_FIQ=in_ThirdWriteBus;
				else if(in_ProcessorMode==`MODE_SVC)
					Registers13_SVC=in_ThirdWriteBus;
				else if(in_ProcessorMode==`MODE_ABT)
					Registers13_ABT=in_ThirdWriteBus;
				else if(in_ProcessorMode==`MODE_IRQ)
					Registers13_IRQ=in_ThirdWriteBus;
				else if(in_ProcessorMode==`MODE_UND)
					Registers13_UND=in_ThirdWriteBus;
				else
					Registers13=in_ThirdWriteBus;
			end
			8'b0000_1110:
			begin
				if(in_MemAccessUserBankRegister2WB==1'b1)
					Registers14=in_ThirdWriteBus;
				if(in_IfChangeState==1'b1)
				begin
					case(in_ChangeStateAction)
					`MODE_FIQ:
						Registers14_FIQ=in_ThirdWriteBus;
					`MODE_SVC:
						Registers14_SVC=in_ThirdWriteBus;
					`MODE_ABT:
						Registers14_ABT=in_ThirdWriteBus;
					`MODE_IRQ:
						Registers14_IRQ=in_ThirdWriteBus;
					`MODE_UND:
						Registers14_UND=in_ThirdWriteBus;
					default:
						Registers14=in_ThirdWriteBus;
					endcase
				end
				else if(in_ProcessorMode==`MODE_FIQ)
					Registers14_FIQ=in_ThirdWriteBus;
				else if(in_ProcessorMode==`MODE_SVC)
					Registers14_SVC=in_ThirdWriteBus;
				else if(in_ProcessorMode==`MODE_ABT)
					Registers14_ABT=in_ThirdWriteBus;
				else if(in_ProcessorMode==`MODE_IRQ)
					Registers14_IRQ=in_ThirdWriteBus;
				else if(in_ProcessorMode==`MODE_UND)
					Registers14_UND=in_ThirdWriteBus;
				else
					Registers14=in_ThirdWriteBus;
			end
			8'b0000_1111:
				Registers15=in_ThirdWriteBus;
			`Def_LocalForwardRegister:
				LocalForwardRegister=in_ThirdWriteBus;
		   endcase
		end

	end
end

endmodule