registerfile.v

若干VHDL语言的源代码

				out_RightReadBus=Registers14;
			if(in_IfChangeState==1'b1)
			begin
				case(in_ChangeStateAction)
				`MODE_FIQ:
					out_RightReadBus=Registers14_FIQ;
				`MODE_SVC:
					out_RightReadBus=Registers14_SVC;
				`MODE_ABT:
					out_RightReadBus=Registers14_ABT;
				`MODE_IRQ:
					out_RightReadBus=Registers14_IRQ;
				`MODE_UND:
					out_RightReadBus=Registers14_UND;
				default:
					out_RightReadBus=Registers14;
				endcase
			end
			else if(in_ProcessorMode==`MODE_FIQ)
				out_RightReadBus=Registers14_FIQ;
			else if(in_ProcessorMode==`MODE_SVC)
				out_RightReadBus=Registers14_SVC;
			else if(in_ProcessorMode==`MODE_ABT)
				out_RightReadBus=Registers14_ABT;
			else if(in_ProcessorMode==`MODE_IRQ)
				out_RightReadBus=Registers14_IRQ;
			else if(in_ProcessorMode==`MODE_UND)
				out_RightReadBus=Registers14_UND;
			else//normal
				out_RightReadBus=Registers14;
		end
		8'b0000_1111:
			out_RightReadBus=Registers15;
		`Def_LocalForwardRegister:
			out_RightReadBus=LocalForwardRegister;
		default:
			out_RightReadBus=`WordZero;
		endcase
	end
	else
	begin
		out_RightReadBus=`WordZero;
	end
end

//third read
always @(Registers0 or
	Registers1 or
	Registers2 or
	Registers3 or
	Registers4 or
	Registers5 or
	Registers6 or
	Registers7 or
	Registers8 or
	Registers9 or
	Registers10 or
	Registers11 or
	Registers12 or
	Registers13 or
	Registers14 or
	Registers15 or
	Registers8_FIQ or
	Registers9_FIQ or
	Registers10_FIQ or
	Registers11_FIQ or
	Registers12_FIQ or
	Registers13_FIQ or
	Registers14_FIQ or
	Registers13_SVC or
	Registers14_SVC or
	Registers13_ABT or
	Registers14_ABT or
	Registers13_IRQ or
	Registers14_IRQ or
	Registers13_UND or
	Registers14_UND or
	LocalForwardRegister or
	in_ProcessorMode or
	in_ThirdReadEnable or
	in_ThirdReadRegisterNumber	or
	in_IfChangeState	or
	in_ChangeStateAction	or
	in_MemAccessUserBankRegister2WB
)
begin
	if(in_ThirdReadEnable==1'b1)
	begin
		case (in_ThirdReadRegisterNumber)
		8'b0000_0000:
			out_ThirdReadBus=Registers0;
		8'b0000_0001:
			out_ThirdReadBus=Registers1;
		8'b0000_0010:
			out_ThirdReadBus=Registers2;
		8'b0000_0011:
			out_ThirdReadBus=Registers3;
		8'b0000_0100:
			out_ThirdReadBus=Registers4;
		8'b0000_0101:
			out_ThirdReadBus=Registers5;
		8'b0000_0110:
			out_ThirdReadBus=Registers6;
		8'b0000_0111:
			out_ThirdReadBus=Registers7;
		8'b0000_1000:
		begin
			if(in_MemAccessUserBankRegister2WB==1'b1)
			begin
				out_ThirdReadBus=Registers8;
			end
			else if(in_ProcessorMode==`MODE_FIQ)
				out_ThirdReadBus=Registers8_FIQ;
			else
				out_ThirdReadBus=Registers8;
		end
		8'b0000_1001:
		begin
			if(in_MemAccessUserBankRegister2WB==1'b1)
			begin
				out_ThirdReadBus=Registers9;
			end
			else if(in_ProcessorMode==`MODE_FIQ)
				out_ThirdReadBus=Registers9_FIQ;
			else
				out_ThirdReadBus=Registers9;
		end
		8'b0000_1010:
		begin
			if(in_MemAccessUserBankRegister2WB==1'b1)
			begin
				out_ThirdReadBus=Registers10;
			end
			else if(in_ProcessorMode==`MODE_FIQ)
				out_ThirdReadBus=Registers10_FIQ;
			else
				out_ThirdReadBus=Registers10;
		end
		8'b0000_1011:
		begin
			if(in_MemAccessUserBankRegister2WB==1'b1)
			begin
				out_ThirdReadBus=Registers11;
			end
			else if(in_ProcessorMode==`MODE_FIQ)
				out_ThirdReadBus=Registers11_FIQ;
			else
				out_ThirdReadBus=Registers11;
		end
		8'b0000_1100:
		begin
			if(in_MemAccessUserBankRegister2WB==1'b1)
			begin
				out_ThirdReadBus=Registers12;
			end
			else if(in_ProcessorMode==`MODE_FIQ)
				out_ThirdReadBus=Registers12_FIQ;
			else
				out_ThirdReadBus=Registers12;
		end
		8'b0000_1101:
		begin
			if(in_MemAccessUserBankRegister2WB==1'b1)
			begin
				out_ThirdReadBus=Registers13;
			end
			else if(in_ProcessorMode==`MODE_FIQ)
				out_ThirdReadBus=Registers13_FIQ;
			else if(in_ProcessorMode==`MODE_SVC)
				out_ThirdReadBus=Registers13_SVC;
			else if(in_ProcessorMode==`MODE_ABT)
				out_ThirdReadBus=Registers13_ABT;
			else if(in_ProcessorMode==`MODE_IRQ)
				out_ThirdReadBus=Registers13_IRQ;
			else if(in_ProcessorMode==`MODE_UND)
				out_ThirdReadBus=Registers13_UND;
			else//normal
				out_ThirdReadBus=Registers13;
		end
		8'b0000_1110:
		begin
			if(in_MemAccessUserBankRegister2WB==1'b1)
				out_ThirdReadBus=Registers14;
			if(in_IfChangeState==1'b1)
			begin
				case(in_ChangeStateAction)
				`MODE_FIQ:
					out_ThirdReadBus=Registers14_FIQ;
				`MODE_SVC:
					out_ThirdReadBus=Registers14_SVC;
				`MODE_ABT:
					out_ThirdReadBus=Registers14_ABT;
				`MODE_IRQ:
					out_ThirdReadBus=Registers14_IRQ;
				`MODE_UND:
					out_ThirdReadBus=Registers14_UND;
				default:
					out_ThirdReadBus=Registers14;
				endcase
			end
			else if(in_ProcessorMode==`MODE_FIQ)
				out_ThirdReadBus=Registers14_FIQ;
			else if(in_ProcessorMode==`MODE_SVC)
				out_ThirdReadBus=Registers14_SVC;
			else if(in_ProcessorMode==`MODE_ABT)
				out_ThirdReadBus=Registers14_ABT;
			else if(in_ProcessorMode==`MODE_IRQ)
				out_ThirdReadBus=Registers14_IRQ;
			else if(in_ProcessorMode==`MODE_UND)
				out_ThirdReadBus=Registers14_UND;
			else//normal
				out_ThirdReadBus=Registers14;
		end
		8'b0000_1111:
			out_ThirdReadBus=Registers15;
		`Def_LocalForwardRegister:
			out_ThirdReadBus=LocalForwardRegister;
		default:
			out_ThirdReadBus=`WordZero;
		endcase
	end
	else
	begin
		out_ThirdReadBus=`WordZero;
	end
end

//fourth read
always @(Registers0 or
	Registers1 or
	Registers2 or
	Registers3 or
	Registers4 or
	Registers5 or
	Registers6 or
	Registers7 or
	Registers8 or
	Registers9 or
	Registers10 or
	Registers11 or
	Registers12 or
	Registers13 or
	Registers14 or
	Registers15 or
	Registers8_FIQ or
	Registers9_FIQ or
	Registers10_FIQ or
	Registers11_FIQ or
	Registers12_FIQ or
	Registers13_FIQ or
	Registers14_FIQ or
	Registers13_SVC or
	Registers14_SVC or
	Registers13_ABT or
	Registers14_ABT or
	Registers13_IRQ or
	Registers14_IRQ or
	Registers13_UND or
	Registers14_UND or
	LocalForwardRegister or
	in_ProcessorMode or
	in_FourthReadEnable or
	in_FourthReadRegisterNumber	or
	in_IfChangeState	or
	in_ChangeStateAction	or
	in_MemAccessUserBankRegister2WB
)
begin
	if(in_FourthReadEnable==1'b1)
	begin
		case (in_FourthReadRegisterNumber)
		8'b0000_0000:
			out_FourthReadBus=Registers0;
		8'b0000_0001:
			out_FourthReadBus=Registers1;
		8'b0000_0010:
			out_FourthReadBus=Registers2;
		8'b0000_0011:
			out_FourthReadBus=Registers3;
		8'b0000_0100:
			out_FourthReadBus=Registers4;
		8'b0000_0101:
			out_FourthReadBus=Registers5;
		8'b0000_0110:
			out_FourthReadBus=Registers6;
		8'b0000_0111:
			out_FourthReadBus=Registers7;
		8'b0000_1000:
		begin
			if(in_MemAccessUserBankRegister2WB==1'b1)
			begin
				out_FourthReadBus=Registers8;
			end
			else if(in_ProcessorMode==`MODE_FIQ)
				out_FourthReadBus=Registers8_FIQ;
			else
				out_FourthReadBus=Registers8;
		end
		8'b0000_1001:
		begin
			if(in_MemAccessUserBankRegister2WB==1'b1)
			begin
				out_FourthReadBus=Registers9;
			end
			else if(in_ProcessorMode==`MODE_FIQ)
				out_FourthReadBus=Registers9_FIQ;
			else
				out_FourthReadBus=Registers9;
		end
		8'b0000_1010:
		begin
			if(in_MemAccessUserBankRegister2WB==1'b1)
			begin
				out_FourthReadBus=Registers10;
			end
			else if(in_ProcessorMode==`MODE_FIQ)
				out_FourthReadBus=Registers10_FIQ;
			else
				out_FourthReadBus=Registers10;
		end
		8'b0000_1011:
		begin
			if(in_MemAccessUserBankRegister2WB==1'b1)
			begin
				out_FourthReadBus=Registers11;
			end
			else if(in_ProcessorMode==`MODE_FIQ)
				out_FourthReadBus=Registers11_FIQ;
			else
				out_FourthReadBus=Registers11;
		end
		8'b0000_1100:
		begin
			if(in_MemAccessUserBankRegister2WB==1'b1)
			begin
				out_FourthReadBus=Registers12;
			end
			else if(in_ProcessorMode==`MODE_FIQ)
				out_FourthReadBus=Registers12_FIQ;
			else
				out_FourthReadBus=Registers12;
		end
		8'b0000_1101:
		begin
			if(in_MemAccessUserBankRegister2WB==1'b1)
			begin
				out_FourthReadBus=Registers13;
			end
			else if(in_ProcessorMode==`MODE_FIQ)
				out_FourthReadBus=Registers13_FIQ;
			else if(in_ProcessorMode==`MODE_SVC)
				out_FourthReadBus=Registers13_SVC;
			else if(in_ProcessorMode==`MODE_ABT)
				out_FourthReadBus=Registers13_ABT;
			else if(in_ProcessorMode==`MODE_IRQ)
				out_FourthReadBus=Registers13_IRQ;
			else if(in_ProcessorMode==`MODE_UND)
				out_FourthReadBus=Registers13_UND;
			else//normal
				out_FourthReadBus=Registers13;
		end
		8'b0000_1110:
		begin
			if(in_MemAccessUserBankRegister2WB==1'b1)
				out_FourthReadBus=Registers14;
			if(in_IfChangeState==1'b1)
			begin
				case(in_ChangeStateAction)
				`MODE_FIQ:
					out_FourthReadBus=Registers14_FIQ;
				`MODE_SVC:
					out_FourthReadBus=Registers14_SVC;
				`MODE_ABT:
					out_FourthReadBus=Registers14_ABT;
				`MODE_IRQ:
					out_FourthReadBus=Registers14_IRQ;
				`MODE_UND:
					out_FourthReadBus=Registers14_UND;
				default:
					out_FourthReadBus=Registers14;
				endcase
			end
			else if(in_ProcessorMode==`MODE_FIQ)
				out_FourthReadBus=Registers14_FIQ;
			else if(in_ProcessorMode==`MODE_SVC)
				out_FourthReadBus=Registers14_SVC;
			else if(in_ProcessorMode==`MODE_ABT)
				out_FourthReadBus=Registers14_ABT;
			else if(in_ProcessorMode==`MODE_IRQ)
				out_FourthReadBus=Registers14_IRQ;
			else if(in_ProcessorMode==`MODE_UND)
				out_FourthReadBus=Registers14_UND;
			else//normal
				out_FourthReadBus=Registers14;
		end
		8'b0000_1111:
			out_FourthReadBus=Registers15;
		`Def_LocalForwardRegister:
			out_FourthReadBus=LocalForwardRegister;
		default:
			out_FourthReadBus=`WordZero;
		endcase
	end
	else
	begin
		out_FourthReadBus=`WordZero;
	end
end



always @(posedge clock or negedge reset)
begin
	if(reset==1'b0)
	begin
		//initial the register file
		Registers0=`WordZero;
		Registers1=`WordZero;
		Registers2=`WordZero;
		Registers3=`WordZero;
		Registers4=`WordZero;
		Registers5=`WordZero;
		Registers6=`WordZero;
		Registers7=`WordZero;
		Registers8=`WordZero;
		Registers9=`WordZero;
		Registers10=`WordZero;
		Registers11=`WordZero;
		Registers12=`WordZero;
		Registers13=`WordZero;
		Registers14=`WordZero;