datacachecontroller.v

若干VHDL语言的源代码

						MemoryOutTmp=`WordZ;
						MemoryOutTmp2Bus=1'b0;

						//up to pipeline
						out_DataCacheWait=1'b1;

						//down to memory
						out_DataMemoryAddress={RIAddress[`AddressBusWidth-1:4],Next_RIWordCount,2'b00};
						out_DataMemoryEnable=1'b1;
						out_DataMemoryRW=1'b1;

						//write and read word count
						WBWordCount=2'b00;
						RIWordCount=Next_RIWordCount;

						//write back and read in address
						WBAddress=`AddressBusZero;

						HaveWait=1'b0;
					end
				end//HaveWait==1'b1
				else
				begin
					//nothing to do
					State=`DCacheState_ReadIn;
				end//HaveWait!=1'b1
			end//in_DataMemoryWait!=1'b1
		end//DCacheState_ReadIn

		`DCacheState_WriteBack:
		begin
			//miss and write back
			if(in_DataMemoryWait==1'b1)
			begin
				//memory is busy
				HaveWait=1'b1;
			end//in_DataMemoryWait==1'b1
			else
			begin
				//in_DataMemoryWait!=1'b1
				if(HaveWait==1'b1)
				begin
					if(Next_WBWordCount==2'b00)
					begin
						//write back end
						State=`DCacheState_Idel;
						Valid[{WBAddress[5:4],ReplaceEntry[WBAddress[5:4]]}]=1'b0;
						Tag[{WBAddress[5:4],ReplaceEntry[WBAddress[5:4]]}]=26'b0000_0000_0000_0000_0000_0000_00;

						DCacheOutTmp=`WordZ;
						DCacheOutTmp2Bus=1'b0;

						//out put the word to be write back
						MemoryOutTmp=`WordZ;
						MemoryOutTmp2Bus=1'b0;


						//up to pipeline
						out_DataCacheWait=1'b1;

						//down to memory
						out_DataMemoryAddress=`AddressBusZ;
						out_DataMemoryEnable=1'b0;
						out_DataMemoryRW=1'b0;

						//write and read word count
						WBWordCount=2'b00;
						RIWordCount=2'b00;

						//write back and read in address
						WBAddress=`AddressBusZero;
						RIAddress=`AddressBusZero;

						HaveWait=1'b0;
					end
					else
					begin
						//write back not end yet
						//state machine
						State=`DCacheState_WriteBack;

						//inout manage
						DCacheOutTmp=`WordZ;
						DCacheOutTmp2Bus=1'b0;

						//out put the word to be write back
						MemoryOutTmp={Mem[{WBAddress[5:4],ReplaceEntry[WBAddress[5:4]],Next_WBWordCount,2'b11}],Mem[{in_DataCacheAddress[5:4],ReplaceEntry[WBAddress[5:4]],WBWordCount,2'b10}],Mem[{in_DataCacheAddress[5:4],ReplaceEntry[WBAddress[5:4]],WBWordCount,2'b01}],Mem[{in_DataCacheAddress[5:4],ReplaceEntry[WBAddress[5:4]],WBWordCount,2'b00}]};
						MemoryOutTmp2Bus=1'b1;

						//up to pipeline
						out_DataCacheWait=1'b1;

						//down to memory
						out_DataMemoryAddress={WBAddress[`AddressBusWidth-1:4],Next_WBWordCount,2'b00};
						out_DataMemoryEnable=1'b1;
						out_DataMemoryRW=1'b0;

						//write and read word count
						WBWordCount=Next_WBWordCount;
						RIWordCount=2'b00;

						//write back and read in address
						RIAddress=`AddressBusZero;

						HaveWait=1'b0;
					end
				end//HaveWait==1'b1
				else
				begin
					//nothing to do
					State=`DCacheState_WriteBack;
				end//HaveWait!=1'b1
			end//in_DataMemoryWait!=1'b1
		end//DCacheState_WriteBack
		endcase
	end
end


//CAM compare
always @(in_DataCacheAddress or
	Tag[0]	or
	Tag[1]	or
	Tag[2]	or
	Tag[3]	or
	Tag[4]	or
	Tag[5]	or
	Tag[6]	or
	Tag[7]	or
	Tag[8]	or
	Tag[9]	or
	Tag[10]	or
	Tag[11]	or
	Tag[12]	or
	Tag[13]	or
	Tag[14]	or
	Tag[15]	or
	Valid[0]	or
	Valid[1]	or
	Valid[2]	or
	Valid[3]	or
	Valid[4]	or
	Valid[5]	or
	Valid[6]	or
	Valid[7]	or
	Valid[8]	or
	Valid[9]	or
	Valid[10]	or
	Valid[11]	or
	Valid[12]	or
	Valid[13]	or
	Valid[14]	or
	Valid[15]	or
	PrevAccess[0]	or
	PrevAccess[1]	or
	PrevAccess[2]	or
	PrevAccess[3]
)
begin
	ReplaceContent[2'b00]=Tag[0];
	ReplaceContent[2'b01]=Tag[4];
	ReplaceContent[2'b10]=Tag[8];
	ReplaceContent[2'b11]=Tag[12];

	if(in_DataCacheAddress[`AddressBusWidth-1:6]==Tag[0]  && in_DataCacheAddress[5:4]==2'b00 && Valid[0]==1'b1)
	begin
		CAMMatch=1'b1;
		CAMEntry=2'b00;
		ReplaceContent[2'b00]=Tag[0];
	end
	else if(in_DataCacheAddress[`AddressBusWidth-1:6]==Tag[1]  && in_DataCacheAddress[5:4]==2'b00 && Valid[1]==1'b1)
	begin
		CAMMatch=1'b1;
		CAMEntry=2'b01;
		ReplaceContent[2'b00]=Tag[1];
	end
	else if(in_DataCacheAddress[`AddressBusWidth-1:6]==Tag[2]  && in_DataCacheAddress[5:4]==2'b00 && Valid[2]==1'b1)
	begin
		CAMMatch=1'b1;
		CAMEntry=2'b10;
		ReplaceContent[2'b00]=Tag[2];
	end
	else if(in_DataCacheAddress[`AddressBusWidth-1:6]==Tag[3]  && in_DataCacheAddress[5:4]==2'b00 && Valid[3]==1'b1)
	begin
		CAMMatch=1'b1;
		CAMEntry=2'b11;
		ReplaceContent[2'b00]=Tag[3];
	end
	else if(in_DataCacheAddress[`AddressBusWidth-1:6]==Tag[4]  && in_DataCacheAddress[5:4]==2'b01 && Valid[4]==1'b1)
	begin
		CAMMatch=1'b1;
		CAMEntry=2'b00;
		ReplaceContent[2'b01]=Tag[4];
	end
	else if(in_DataCacheAddress[`AddressBusWidth-1:6]==Tag[5]  && in_DataCacheAddress[5:4]==2'b01 && Valid[5]==1'b1)
	begin
		CAMMatch=1'b1;
		CAMEntry=2'b01;
		ReplaceContent[2'b01]=Tag[5];
	end
	else if(in_DataCacheAddress[`AddressBusWidth-1:6]==Tag[6]  && in_DataCacheAddress[5:4]==2'b01 && Valid[6]==1'b1)
	begin
		CAMMatch=1'b1;
		CAMEntry=2'b10;
		ReplaceContent[2'b01]=Tag[6];
	end
	else if(in_DataCacheAddress[`AddressBusWidth-1:6]==Tag[7]  && in_DataCacheAddress[5:4]==2'b01 && Valid[7]==1'b1)
	begin
		CAMMatch=1'b1;
		CAMEntry=2'b11;
		ReplaceContent[2'b01]=Tag[7];
	end
	else if(in_DataCacheAddress[`AddressBusWidth-1:6]==Tag[8]  && in_DataCacheAddress[5:4]==2'b10 && Valid[8]==1'b1)
	begin
		CAMMatch=1'b1;
		CAMEntry=2'b00;
		ReplaceContent[2'b10]=Tag[8];
	end
	else if(in_DataCacheAddress[`AddressBusWidth-1:6]==Tag[9]  && in_DataCacheAddress[5:4]==2'b10 && Valid[9]==1'b1)
	begin
		CAMMatch=1'b1;
		CAMEntry=2'b01;
		ReplaceContent[2'b10]=Tag[9];
	end
	else if(in_DataCacheAddress[`AddressBusWidth-1:6]==Tag[10]  && in_DataCacheAddress[5:4]==2'b10 && Valid[10]==1'b1)
	begin
		CAMMatch=1'b1;
		CAMEntry=2'b10;
		ReplaceContent[2'b10]=Tag[10];
	end
	else if(in_DataCacheAddress[`AddressBusWidth-1:6]==Tag[11]  && in_DataCacheAddress[5:4]==2'b10 && Valid[11]==1'b1)
	begin
		CAMMatch=1'b1;
		CAMEntry=2'b11;
		ReplaceContent[2'b10]=Tag[11];
	end
	else if(in_DataCacheAddress[`AddressBusWidth-1:6]==Tag[12]  && in_DataCacheAddress[5:4]==2'b11 && Valid[12]==1'b1)
	begin
		CAMMatch=1'b1;
		CAMEntry=2'b00;
		ReplaceContent[2'b11]=Tag[12];
	end
	else if(in_DataCacheAddress[`AddressBusWidth-1:6]==Tag[13]  && in_DataCacheAddress[5:4]==2'b11 && Valid[13]==1'b1)
	begin
		CAMMatch=1'b1;
		CAMEntry=2'b01;
		ReplaceContent[2'b11]=Tag[13];
	end
	else if(in_DataCacheAddress[`AddressBusWidth-1:6]==Tag[14]  && in_DataCacheAddress[5:4]==2'b11 && Valid[14]==1'b1)
	begin
		CAMMatch=1'b1;
		CAMEntry=2'b10;
		ReplaceContent[2'b11]=Tag[14];
	end
	else if(in_DataCacheAddress[`AddressBusWidth-1:6]==Tag[15]  && in_DataCacheAddress[5:4]==2'b11 && Valid[15]==1'b1)
	begin
		CAMMatch=1'b1;
		CAMEntry=2'b11;
		ReplaceContent[2'b11]=Tag[15];
	end
	else 
	begin
		CAMMatch=1'b0;
		CAMEntry=2'b00;
	end

	//decide which entry of section0 can be replace
	if(Valid[0]==1'b0)
	begin
		ReplaceEntry[0]=2'b00;
	end
	else if(Valid[1]==1'b0)
	begin
		ReplaceEntry[0]=2'b01;
	end
	else if(Valid[2]==1'b0)
	begin
		ReplaceEntry[0]=2'b10;
	end
	else if(Valid[3]==1'b0)
	begin
		ReplaceEntry[0]=2'b11;
	end
	else
	begin
		ReplaceEntry[0]=2'b00;
		case (PrevAccess[0])
		2'b00:
			ReplaceEntry[0]=2'b01;
		2'b01:
			ReplaceEntry[0]=2'b10;
		2'b10:
			ReplaceEntry[0]=2'b11;
		2'b11:
			ReplaceEntry[0]=2'b00;
		endcase
	end

	//decide which entry of section1 can be replace
	if(Valid[4]==1'b0)
	begin
		ReplaceEntry[1]=2'b00;
	end
	else if(Valid[5]==1'b0)
	begin
		ReplaceEntry[1]=2'b01;
	end
	else if(Valid[6]==1'b0)
	begin
		ReplaceEntry[1]=2'b10;
	end
	else if(Valid[7]==1'b0)
	begin
		ReplaceEntry[1]=2'b11;
	end
	else
	begin
		ReplaceEntry[1]=2'b00;
		case (PrevAccess[1])
		2'b00:
			ReplaceEntry[1]=2'b01;
		2'b01:
			ReplaceEntry[1]=2'b10;
		2'b10:
			ReplaceEntry[1]=2'b11;
		2'b11:
			ReplaceEntry[1]=2'b00;
		endcase
	end

	//decide which entry of section2 can be replace
	if(Valid[8]==1'b0)
	begin
		ReplaceEntry[2]=2'b00;
	end
	else if(Valid[9]==1'b0)
	begin
		ReplaceEntry[2]=2'b01;
	end
	else if(Valid[10]==1'b0)
	begin
		ReplaceEntry[2]=2'b10;
	end
	else if(Valid[11]==1'b0)
	begin
		ReplaceEntry[2]=2'b11;
	end
	else
	begin
		ReplaceEntry[2]=2'b00;
		case (PrevAccess[2])
		2'b00:
			ReplaceEntry[2]=2'b01;
		2'b01:
			ReplaceEntry[2]=2'b10;
		2'b10:
			ReplaceEntry[2]=2'b11;
		2'b11:
			ReplaceEntry[2]=2'b00;
		endcase
	end

	//decide which entry of section3 can be replace
	if(Valid[12]==1'b0)
	begin
		ReplaceEntry[3]=2'b00;
	end
	else if(Valid[13]==1'b0)
	begin
		ReplaceEntry[3]=2'b01;
	end
	else if(Valid[14]==1'b0)
	begin
		ReplaceEntry[3]=2'b10;
	end
	else if(Valid[15]==1'b0)
	begin
		ReplaceEntry[3]=2'b11;
	end
	else
	begin
		ReplaceEntry[3]=2'b00;
		case (PrevAccess[3])
		2'b00:
			ReplaceEntry[3]=2'b01;
		2'b01:
			ReplaceEntry[3]=2'b10;
		2'b10:
			ReplaceEntry[3]=2'b11;
		2'b11:
			ReplaceEntry[3]=2'b00;
		endcase
	end

end


//deal with word count increase
always @(WBWordCount)
begin
	Next_WBWordCount=2'b00;
	case (WBWordCount)
	2'b11:
		Next_WBWordCount=2'b00;
	2'b10:
		Next_WBWordCount=2'b11;
	2'b01:
		Next_WBWordCount=2'b10;
	2'b00:
		Next_WBWordCount=2'b01;
	endcase 
end

always @(RIWordCount)
begin
	Next_RIWordCount=2'b00;
	case (RIWordCount)
	2'b11:
		Next_RIWordCount=2'b00;
	2'b10:
		Next_RIWordCount=2'b11;
	2'b01:
		Next_RIWordCount=2'b10;
	2'b00:
		Next_RIWordCount=2'b01;
	endcase 
end

endmodule