instructioncachecontroller.v

若干VHDL语言的源代码

					end
				8'b0000_0010:
					begin
						WordCount=8'b0000_0011;
						LineStore[63:32]=MemoryBus;
						//continue to send out request
						MemoryAddress={InstructionAddress[`AddressBusWidth-1:4],4'b1000};
						MemoryRequest=1'b1;
					end
				8'b0000_0011:
					begin
						WordCount=8'b0000_0100;
						LineStore[95:64]=MemoryBus;
						//continue to send out request
						MemoryAddress={InstructionAddress[`AddressBusWidth-1:4],4'b1100};
						MemoryRequest=1'b1;
					end
				8'b0000_0100:
					begin
						WordCount=`ByteZero;
						LineStore[127:96]=MemoryBus;
						//NOTE: store LineStore to cache line
						//enable the V and tag
						MemoryRequest=1'b0;
						Status=`InstructionCacheMemoryAccess_Normal;
						//$monitor($time,"		fetch back from memory at:	%h",AddressStore);
						case (AddressStore[5:4])
						2'b00:	//section0
							begin
								if(V00==1'b0)
								begin
									//line0 is blank
									V00=1'b1;
									tag00=AddressStore;
									S0_L0=LineStore;
									PrevAccess0=2'b00;
								end
								else if(V01==1'b0)
								begin
									//line1 is blank
									V01=1'b1;
									tag01=AddressStore;
									S0_L1=LineStore;
									PrevAccess0=2'b01;
								end
								else if(V02==1'b0)
								begin
									//line2 is blank
									V02=1'b1;
									tag02=AddressStore;
									S0_L2=LineStore;
									PrevAccess0=2'b10;
								end
								else if(V03==1'b0)
								begin
									//line3 is blank
									V03=1'b1;
									tag03=AddressStore;
									S0_L3=LineStore;
									PrevAccess0=2'b11;
								end
								else
								begin
									//none avilable
									case (PrevAccess0)
									2'b00:
										begin
											V01=1'b1;
											tag01=AddressStore;
											S0_L1=LineStore;
											PrevAccess0=2'b01;
										end
									2'b01:
										begin
											V02=1'b1;
											tag02=AddressStore;
											S0_L2=LineStore;
											PrevAccess0=2'b10;
										end
									2'b10:
										begin
											V03=1'b1;
											tag03=AddressStore;
											S0_L3=LineStore;
											PrevAccess0=2'b11;
										end
									2'b11:
										begin
											V00=1'b1;
											tag00=AddressStore;
											S0_L0=LineStore;
											PrevAccess0=2'b00;
										end
									endcase
								end
							end
						2'b01:	//section1
							begin
								if(V10==1'b0)
								begin
									//line0 is blank
									V10=1'b1;
									tag10=AddressStore;
									S1_L0=LineStore;
									PrevAccess1=2'b00;
								end
								else if(V11==1'b0)
								begin
									//line1 is blank
									V11=1'b1;
									tag11=AddressStore;
									S1_L1=LineStore;
									PrevAccess1=2'b01;
								end
								else if(V12==1'b0)
								begin
									//line2 is blank
									V12=1'b1;
									tag12=AddressStore;
									S1_L2=LineStore;
									PrevAccess1=2'b10;
								end
								else if(V13==1'b0)
								begin
									//line3 is blank
									V13=1'b1;
									tag13=AddressStore;
									S1_L3=LineStore;
									PrevAccess1=2'b11;
								end
								else
								begin
									//none avilable
									case (PrevAccess1)
									2'b00:
										begin
											V11=1'b1;
											tag11=AddressStore;
											S1_L1=LineStore;
											PrevAccess1=2'b01;
										end
									2'b01:
										begin
											V12=1'b1;
											tag12=AddressStore;
											S1_L2=LineStore;
											PrevAccess1=2'b10;
										end
									2'b10:
										begin
											V13=1'b1;
											tag13=AddressStore;
											S1_L3=LineStore;
											PrevAccess1=2'b11;
										end
									2'b11:
										begin
											V10=1'b1;
											tag10=AddressStore;
											S1_L0=LineStore;
											PrevAccess1=2'b00;
										end
									endcase
								end
							end

						2'b10:	//section2
							begin
								if(V20==1'b0)
								begin
									//line0 is blank
									V20=1'b1;
									tag20=AddressStore;
									S2_L0=LineStore;
									PrevAccess2=2'b00;
								end
								else if(V21==1'b0)
								begin
									//line1 is blank
									V21=1'b1;
									tag21=AddressStore;
									S2_L1=LineStore;
									PrevAccess2=2'b01;
								end
								else if(V22==1'b0)
								begin
									//line2 is blank
									V22=1'b1;
									tag22=AddressStore;
									S2_L2=LineStore;
									PrevAccess2=2'b10;
								end
								else if(V23==1'b0)
								begin
									//line3 is blank
									V23=1'b1;
									tag23=AddressStore;
									S2_L3=LineStore;
									PrevAccess2=2'b11;
								end
								else
								begin
									//none avilable
									case (PrevAccess2)
									2'b00:
										begin
											V21=1'b1;
											tag21=AddressStore;
											S2_L1=LineStore;
											PrevAccess2=2'b01;
										end
									2'b01:
										begin
											V22=1'b1;
											tag22=AddressStore;
											S2_L2=LineStore;
											PrevAccess2=2'b10;
										end
									2'b10:
										begin
											V23=1'b1;
											tag23=AddressStore;
											S2_L3=LineStore;
											PrevAccess2=2'b11;
										end
									2'b11:
										begin
											V20=1'b1;
											tag20=AddressStore;
											S2_L0=LineStore;
											PrevAccess2=2'b00;
										end
									endcase
								end
							end

						2'b11:	//section3
							begin
								if(V30==1'b0)
								begin
									//line0 is blank
									V30=1'b1;
									tag30=AddressStore;
									S3_L0=LineStore;
									PrevAccess3=2'b00;
								end
								else if(V31==1'b0)
								begin
									//line1 is blank
									V31=1'b1;
									tag31=AddressStore;
									S3_L1=LineStore;
									PrevAccess3=2'b01;
								end
								else if(V32==1'b0)
								begin
									//line2 is blank
									V32=1'b1;
									tag32=AddressStore;
									S3_L2=LineStore;
									PrevAccess3=2'b10;
								end
								else if(V33==1'b0)
								begin
									//line3 is blank
									V33=1'b1;
									tag33=AddressStore;
									S3_L3=LineStore;
									PrevAccess3=2'b11;
								end
								else
								begin
									//none avilable
									case (PrevAccess3)
									2'b00:
										begin
											V31=1'b1;
											tag31=AddressStore;
											S3_L1=LineStore;
											PrevAccess3=2'b01;
										end
									2'b01:
										begin
											V32=1'b1;
											tag32=AddressStore;
											S3_L2=LineStore;
											PrevAccess3=2'b10;
										end
									2'b10:
										begin
											V33=1'b1;
											tag33=AddressStore;
											S3_L3=LineStore;
											PrevAccess3=2'b11;
										end
									2'b11:
										begin
											V30=1'b1;
											tag30=AddressStore;
											S3_L0=LineStore;
											PrevAccess3=2'b00;
										end
									endcase
								end
							end

						endcase
					end
				endcase
			end
		endcase
	end
end


endmodule