📄 thumb_2_nnarm.v
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/************************************************************************\
**************************************************************************
**************************************************************************
**************************************************************************
**************************************************************************
*******+---------------------------------------------------------+********
*******|+-------------------------------------------------------+|********
*******||| |||********
*******||| Project : nnARM |||********
*******||| Module : thumb_2_nnarm |||********
*******||| Designer : Mian |||********
*******||| Date : 11 July 2001 |||********
*******||| Abstract : Converts 16 bit Thumb Instructions into |||********
*******||| 32 Bit nnARM Instructions. |||********
*******||| Ver : 0.2 |||********
*******||| Comments : |||********
*******||| Long Branches are not supported |||********
*******||| For Undefined Inst,cond field is 4'b1111|||********
*******||| |||********
*******|+-------------------------------------------------------+|********
*******+---------------------------------------------------------+********
**************************************************************************
**************************************************************************
**************************************************************************
**************************************************************************
\************************************************************************/
module thumb_2_nnarm (
//INPUTS
in_AddressGoWithInstruction,
cti , //Current THUMB Instruction
reset ,
clock ,
//OUTPUTS
out_ClearBit1, //ssy add 2001 7 19
out_AddressOfFirstHalf,//half word align, so bit 0 will be use to indicate whether there is a long branch with link
arm_inst,
//clear internal state
in_ChangePC,
in_MEMChangePC
);// nnARM Instruction
//-----------------------------------------------------------//
// INPUTS //
//-----------------------------------------------------------//
input [`AddressBusWidth-1:0] in_AddressGoWithInstruction;
input [15:0] cti ;
input clock ;
input reset ;
input in_ChangePC,in_MEMChangePC;
//-----------------------------------------------------------//
// OUTPUTS //
//-----------------------------------------------------------//
output [`AddressBusWidth-1:0] out_AddressOfFirstHalf;
output out_ClearBit1; //ssy add 2001 7 19
output [31:0] arm_inst ;
//-----------------------------------------------------------//
// REGISTERS & WIRES //
//-----------------------------------------------------------//
reg ClearBit1; //ssy add 2001 7 19
reg [27:0] t2a ;
reg [3:0] cond ;
reg wb_check ;
wire [1:0] op0 ;
wire op1 ;
wire l_bit ;
wire select_bit ;
//long branch with link state
//ssy add 2001 7 20
reg [10:0] LongBranchWithLinkOff;
//next state of LongBranchWithLinkOff
reg [10:0] Next_LongBranchWithLinkOff;
reg [`AddressBusWidth-1:0] AddressOfFirstHalf;
reg [`AddressBusWidth-1:0] Next_AddressOfFirstHalf;
assign out_ClearBit1=ClearBit1; //ssy add 2001 7 19
assign out_AddressOfFirstHalf=AddressOfFirstHalf;
//-----------------------------------------------------------//
// CONDITION //
//-----------------------------------------------------------//
always@(cti) //if async block is required
/*always@(posedge clock or negedge reset) //if sync block is required
if(reset)
cond <= 4'b0000 ;
else */ if(cti[15:12] == 4'b1101) //Conditional Branches
begin
if(cti[11:8] == 4'b1111) //SSY NOTE: SWI instruction
cond <= 4'b1110 ;
else if(cti[11:8] == 4'b1110) //SSY NOTE: never be use
cond <= 4'b1111 ;
else
cond <= cti[11:8] ;
end
//+++++++++++++++++++++//
else if((cti[15:13] == 3'b010) & (~(| cti[12:11]) & cti[10]) ) //format 5.5 SSY NOTE:Hi reg operation or BX
begin
if(cti[9] & cti[8]) //SSY NOTE:BX
cond <= {3'b111,cti[7]} ;//SSY NOTE: in this case cti[7] is always 1'b0,means ALWAYS run this instruction
else //SSY NOTE:Hi reg operation
cond <= {3'b111,( ~( cti[7] | cti[6] ))} ; // SSY NOTE:~(cti[6] | cti[7]) is always 0, so ALWAYS Run
end
//+++++++++++++++++++++//
else
cond <= 4'b1110 ; //ALWAYS
//-----------------------------------------------------------//
// OpCode //
//-----------------------------------------------------------//
assign op0 = ~( cti[12:11] ) ;
assign op1 = ~( cti[12] | cti[11]) ;//SSY NOTE: 12 and 11 is 00
assign l_bit = ( cti[11] | cti[10]) ;//SSY NOTE: 11 and 10 is 11 10 01 means load when cti is a compressed load/store sign data
assign select_bit = (~l_bit | cti[11]) ;//SSY NOTE 11 and 10 is 00 10 11
always@(cti) //for multiple load write back only when base is
//not in list
//changed in ver 0.2
begin
case(cti[10:8])
3'b000 : wb_check <= ~cti[0];
3'b001 : wb_check <= ~cti[1];
3'b010 : wb_check <= ~cti[2];
3'b011 : wb_check <= ~cti[3];
3'b100 : wb_check <= ~cti[4];
3'b101 : wb_check <= ~cti[5];
3'b110 : wb_check <= ~cti[6];
3'b111 : wb_check <= ~cti[7];
endcase
end
always@(cti or op0 or op1 or l_bit or select_bit or wb_check) //if async block
/*always@(posedge clock or negedge reset) //if sync block
if(reset)
t2a <= 28'b0; ;
else */
begin
//to prevent latch infer
ClearBit1=1'b0; //ssy add 2001 7 19
Next_LongBranchWithLinkOff=11'b0000_0000_000;//ssy add 2001 7 20
Next_AddressOfFirstHalf=`AddressBusZero;//ssy add 2001 7 20
case(cti[15:13])
3'b000 : begin
if(cti[12] & cti[11]) //Add/Subtract
t2a <= {2'b00, //ARM data processing instruction [27:26] is always 00
cti[10], //Immediate value
1'b0,~cti[9],cti[9],1'b0,//opcode 0010 is sub , 0100 is add
1'b1, //set condition code
1'b0,cti[5:3], //Rn -- first operand
1'b0,cti[2:0], //Rd -- second operand
9'b000000000,cti[8:6]}; //3 bits extend to 12 bit offset
else //Move Shifted Register
t2a <= {2'b00, //ARM data processing instruction [27:26] is always 00
1'b0, //op2 is from register
4'b1101, //mov
1'b1, //set condition code
4'b0000, //op1 that do not use here
1'b0,cti[2:0], //destination register
cti[10:6], //shift ammount
cti[12:11], //shift type
1'b0, //no use here
1'b0,cti[5:3]}; //the op2
end
//+++++++++++++++++++++//
3'b001 : begin //Move/Compare/Add/Subtract immediate
case(cti[12:11])
//move
2'b00 : t2a <= {2'b00, //ARM data processing instruction [27:26] is always 00
1'b1, //immediate value
op0,cti[11],op1,//1101 is mov
1'b1, //set condition code
4'b0000, //op1 do not use here
1'b0,cti[10:8], //target register
4'b0000,cti[7:0]};//extend 8bit imm to 12 bits
//cmp
2'b01 : t2a <= {2'b00, //ARM data processing instruction [27:26] is always 00
1'b1, //immediate value
op0,cti[11],op1,//1010 is cmp
1'b1, //set condition code
1'b0,cti[10:8], //op1
4'b0000, //no target
4'b0000,cti[7:0]};//extend 8bit imm to 12 bits
//add
2'b10 : t2a <= {2'b00, //ARM data processing instruction [27:26] is always 00
1'b1, //immediate value
op0,cti[11],op1,//0100 is add
1'b1, //set condition code
1'b0,cti[10:8], //op1
1'b0,cti[10:8], //target register
4'b0000,cti[7:0]};//extend 8 bits to 12 bits
//sub
2'b11 : t2a <= {2'b00, //ARM data processing instruction [27:26] is always 00
1'b1, //immediate value
op0,cti[11],op1,//0010 is sub
1'b1, //set condition code
1'b0,cti[10:8], //op1
1'b0,cti[10:8], //target register
4'b0000,cti[7:0]};//extend 8 bits imm to 12 bits
endcase
end
//+++++++++++++++++++++//
3'b010 : begin
if(cti[12]==1'b1)
begin
if(cti[9]==1'b1) // Load/Store sign-extended byte/halfword
t2a <= {3'b000, //half word and sign data transfer always have [27:25] as 000
1'b1, //pre index, add/sub offset and then transfer
1'b1, //add offset to base
1'b0, //no use here, always is 1'b0
1'b0, //do not write back address
l_bit, //1 means load,else store
1'b0,cti[5:3], //base register
1'b0,cti[2:0], //target register
5'b00001, //no use here, always is this value
cti[10], //S bit
select_bit, //excellent code about H and S bit ,Mian: the code reqired is (~cti[10] | cti[11]).
1'b1, //always this value
1'b0,cti[8:6]}; //offset register
else //Load/Store with Register Offset
t2a <= {2'b01, //always 01
1'b1, //offset is a register
1'b1, //pre index
1'b1, //up , add offset to base
cti[10], //byte or word
1'b0, // do not need write back
cti[11], //load
1'b0,cti[5:3], //base register
1'b0,cti[2:0], //target register
8'h00, //no use here
1'b0,cti[8:6]}; //offset register
end
//\/\/\/\/\/\/\\
else if(cti[11]==1'b1) // PC-Relative Load
begin
t2a <= {2'b01, //always 01
1'b0, //offset is immediate value
1'b1, //pre index
1'b1, //up, add offset to base
1'b0, //transfer word
1'b0, //do not need write back
1'b1, //load
4'b1111, //PC use as base
1'b0,cti[10:8], //target register
2'b00,cti[7:0],2'b00};//offset extend to
ClearBit1=1'b1; //ssy add 2001 7 19
end
//\/\/\/\/\/\/\\
else if(cti[10]==1'b1) // Hi Register Operations/Branch Exchange
case(cti[9:8])
//add
2'b00 : t2a <= {2'b00, //always 00
1'b0, //op2 is a register
4'b0100, //add op
1'b0, //do not set condition code
cti[7],cti[2:0], //op1 and target
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