alushell.v

若干VHDL语言的源代码

		IsLoadToPC=Next_IsLoadToPC;
		
		Valid=Next_Valid;
		
		ALUOwnCanGo=Next_ALUOwnCanGo;

		IfChangeState=Next_IfChangeState;
		ChangeStateAction=Next_ChangeStateAction;

		//delay branch signal
		MEMStoreDelayBranchTarget=Next_MEMStoreDelayBranchTarget;
		MEMDelayBranch=Next_MEMDelayBranch;
		
		MemAccessUserBankRegister=Next_MemAccessUserBankRegister;
	end
end

//determine the next state of pipelne register
//and out_ALUOwnCanGo
always @(in_MEMCanGo		or
		//current state
		Valid			or
		ALUType		or
		LeftOperand		or
		RightOperand	or
		RightShiftType	or
		RightShiftCount	or
		RightShiftCountHighBits	or
		RightShiftCountInReg	or
		Operand2IsReg		or
		TargetRegister	or
		SimpleALUType	or
		SimpleALUTargetRegister	or
		StoredValue	or
		MEMType	or
		MEMTargetRegister	or
		SimpleMEMType	or
		SimpleMEMTargetRegister	or
		CPSR			or
		SPSR			or
		ALUPSRType		or
		MEMPSRType		or
		InstructionCondition	or
		NextAddressGoWithInstruction2ALU	or
		IsBranch		or
		IsLoadToPC		or
		ALUOwnCanGo		or
		IfChangeState		or
		ChangeStateAction	or
		MEMStoreDelayBranchTarget	or
		MEMDelayBranch		or
		MemAccessUserBankRegister	or
		//signal relate to write
		out_ALUWriteEnable or
		out_ALUWriteBus	or		//write result
		out_CPSR	or
		out_SPSR	or
		out_ALUTargetRegister	or	//write to which register
		out_ALUOwnCanGo		or
		out_SimpleALUTargetRegister	or
		out_SimpleALUResult	or
		out_ALUPSRType	or
		out_ChangePC	or
		//below is signal relate to new operation
		in_ALUEnable	or
		in_ALUType		or
		in_ALULeftRegister	or
		in_ALURightRegister	or
		in_ALUThirdRegister	or
		in_ALULeftFromImm		or
		in_ALURightFromImm	or
		in_ALUThirdFromImm	or
		in_CPSRFromImm		or
		in_SPSRFromImm		or
		in_ALURightShiftType	or
		in_ALULeftReadBus		or
		in_ALURightReadBus	or
		in_ALUThirdReadBus	or
		in_ALUCPSRReadBus	or
		in_ALUSPSRReadBus	or
		in_ALUTargetRegister	or
		in_SimpleALUType		or
		in_SimpleALUTargetRegister or
		in_ALUMisc	or
		in_ALUPSRType	or
		in_MEMType			or
		in_MEMTargetRegister	or
		in_SimpleMEMType		or
		in_SimpleMEMTargetRegister	or
		in_MEMPSRType		or
		in_NextAddressGoWithInstruction2ALU	or
		//below is signal relate to forward operand from mem stage
		in_MEMWriteEnable		or
		in_MEMWriteResult		or
		in_MEMCPSR2WB			or
		in_MEMSPSR2WB			or
		in_MEMTargetRegister2WB or
		in_SimpleMEMResult	or
		in_SimpleMEMTargetRegister2WB	or
		in_MEMPSRType2WB	or
		in_MEMChangePC
		)
begin
	if(in_MEMCanGo==1'b1 && out_ALUOwnCanGo==1'b1)
	begin
		//alu can go
		if(in_ALUEnable==1'b1 && out_ChangePC==1'b0 && in_MEMChangePC==1'b0)
		begin
		   if(!(`Def_CurrentALUOperationWantToForwardFromMEMToNextALUOperation))
		   begin
		   	//the current operation in alu do not want to forward to next alu operation from mem
			//new alu operation and previous instruction do not modify pc
			Next_Valid=1'b1;
			Next_ALUType=in_ALUType;
			
			//deal with left operand
			if(in_ALULeftFromImm==1'b1)
			begin
				//left come from immediate
				//read left operand from left bus
				Next_LeftOperand=in_ALULeftReadBus;
			end
			else if(out_ALUWriteEnable==1'b1 && out_ALUTargetRegister==in_ALULeftRegister)
			begin
				//read left operand from ALU output
				Next_LeftOperand=out_ALUWriteBus;
			end
			else if(out_ALUWriteEnable==1'b1 && out_SimpleALUTargetRegister==in_ALULeftRegister)
			begin
				//read left from simple alu output
				Next_LeftOperand=out_SimpleALUResult;
			end
			else if(in_MEMWriteEnable==1'b1 && in_MEMTargetRegister2WB==in_ALULeftRegister)
			begin
				//read left operand from MEM output
				Next_LeftOperand=in_MEMWriteResult;
			end
			else if(in_MEMWriteEnable==1'b1 && in_SimpleMEMTargetRegister2WB==in_ALULeftRegister)
			begin
				//read left from simple MEM output
				Next_LeftOperand=in_SimpleMEMResult;
			end
			else
			begin
				//read left operand from left bus
				Next_LeftOperand=in_ALULeftReadBus;
			end

			Next_Operand2IsReg=~in_ALURightFromImm;
			//deal with right operand
			if(in_ALURightFromImm==1'b1)
			begin
				//Right come from immediate
				//read right operand from right bus
				Next_RightOperand=in_ALURightReadBus;
			end
			else if(out_ALUWriteEnable==1'b1 && out_ALUTargetRegister==in_ALURightRegister)
			begin
				//read Right operand from ALU output
				Next_RightOperand=out_ALUWriteBus;
			end
			else if(out_ALUWriteEnable==1'b1 && out_SimpleALUTargetRegister==in_ALURightRegister)
			begin
				//read right from simple alu output
				Next_RightOperand=out_SimpleALUResult;
			end
			else if(in_MEMWriteEnable==1'b1 && in_MEMTargetRegister2WB==in_ALURightRegister)
			begin
				//read right operand from MEM output
				Next_RightOperand=in_MEMWriteResult;
			end
			else if(in_MEMWriteEnable==1'b1 && in_SimpleMEMTargetRegister2WB==in_ALURightRegister)
			begin
				//read right from simple mem output
				Next_RightOperand=in_SimpleMEMResult;
			end
			else
			begin
				//read right operand from bus
				Next_RightOperand=in_ALURightReadBus;
			end

			Next_RightShiftType=in_ALURightShiftType;

			Next_StoredValue=in_ALUThirdReadBus;
			//deal with shift count
			if(in_ALUMisc[0]==1'b1 || in_ALUType==`ALUType_Mla)
			begin//when there is a mla,then the added operand will be store in storedvalue
				//shift count come from in_ALUMisc
				//current there is only store operation can generate this condition
				//for a store,base come in left register
				//offset come from right register
				//shift count come from in_ALUMisc[5:1]
				//stored value come from third register read
				Next_RightShiftCount=in_ALUMisc[5:1];
				Next_RightShiftCountHighBits=3'b000;
				Next_RightShiftCountInReg=1'b0;
				//deal with forward of stored value
				if(in_ALUThirdFromImm==1'b1)
				begin
					//store value come from imm
					Next_StoredValue=in_ALUThirdReadBus;
				end
				else if(out_ALUWriteEnable==1'b1 && out_ALUTargetRegister==in_ALUThirdRegister)
				begin
					//read stored value from alu output
					Next_StoredValue=out_ALUWriteBus;
				end
				else if(out_ALUWriteEnable==1'b1 && out_SimpleALUTargetRegister==in_ALUThirdRegister)
				begin
					//read stored value from simple alu output
					Next_StoredValue=out_SimpleALUResult;
				end
				else if(in_MEMWriteEnable==1'b1 && in_MEMTargetRegister2WB==in_ALUThirdRegister)
				begin
					//read stored value from mem output
					Next_StoredValue=in_MEMWriteResult;
				end
				else if(in_MEMWriteEnable==1'b1 && in_SimpleMEMTargetRegister2WB==in_ALUThirdRegister)
				begin
					//read stored value from simple mem output
					Next_StoredValue=in_SimpleMEMResult;
				end
				else
				begin
					//read stored valuefrom bus
					Next_StoredValue=in_ALUThirdReadBus;
				end
			end
			else if(in_ALUThirdFromImm==1'b1)
			begin
				//third come from imm
				Next_RightShiftCount=in_ALUThirdReadBus[`Def_ShiftCountWidth-1:0];
				Next_RightShiftCountHighBits=3'b000;
				Next_RightShiftCountInReg=1'b0;
			end
			else if(out_ALUWriteEnable==1'b1 && out_ALUTargetRegister==in_ALUThirdRegister)
			begin
				//read shift count from alu output
				Next_RightShiftCount=out_ALUWriteBus[`Def_ShiftCountWidth-1:0];
				Next_RightShiftCountHighBits=out_ALUWriteBus[7:5];
				Next_RightShiftCountInReg=1'b1;
			end
			else if(out_ALUWriteEnable==1'b1 && out_SimpleALUTargetRegister==in_ALUThirdRegister)
			begin
				//read third from simple alu output
				Next_RightShiftCount=out_SimpleALUResult[`Def_ShiftCountWidth-1:0];
				Next_RightShiftCountHighBits=out_SimpleALUResult[7:5];
				Next_RightShiftCountInReg=1'b1;
			end
			else if(in_MEMWriteEnable==1'b1 && in_MEMTargetRegister2WB==in_ALUThirdRegister)
			begin
				//read shift count from mem output
				Next_RightShiftCount=in_MEMWriteResult[`Def_ShiftCountWidth-1:0];
				Next_RightShiftCountHighBits=in_MEMWriteResult[7:5];
				Next_RightShiftCountInReg=1'b1;
			end
			else if(in_MEMWriteEnable==1'b1 && in_SimpleMEMTargetRegister2WB==in_ALUThirdRegister)
			begin
				//read shift count from simple mem output
				Next_RightShiftCount=in_SimpleMEMResult[`Def_ShiftCountWidth-1:0];
				Next_RightShiftCountHighBits=in_SimpleMEMResult[7:5];
				Next_RightShiftCountInReg=1'b1;
			end
			else
			begin
				//read shift count from bus
				Next_RightShiftCount=in_ALUThirdReadBus[`Def_ShiftCountWidth-1:0];
				Next_RightShiftCountHighBits=in_ALUThirdReadBus[7:5];
				Next_RightShiftCountInReg=1'b1;
			end


			//deal with cpsr forward
			if(in_CPSRFromImm==1'b1)
			begin
				//cpsr is from imm,
				//read it from bus
				//do not forward
				Next_CPSR=in_ALUCPSRReadBus;
			end
			else if(out_ALUWriteEnable==1'b1 && `ALUWriteCPSR)
			begin
				Next_CPSR=out_CPSR;
			end
			else if(in_MEMWriteEnable==1'b1 && `MEMWriteCPSR)
			begin
				Next_CPSR=in_MEMCPSR2WB;
			end
			else
			begin
				//come direct from register without forward
				Next_CPSR=in_ALUCPSRReadBus;
			end

			//deal with spsr forward
			if(in_SPSRFromImm==1'b1)
			begin
				//spsr is from imm,
				//read it from bus
				//do not forward
				Next_SPSR=in_ALUSPSRReadBus;
			end
			else if(out_ALUWriteEnable==1'b1 && `ALUWriteSPSR)
			begin
				Next_SPSR=out_SPSR;
			end
			else if(in_MEMWriteEnable==1'b1 && `MEMWriteSPSR)
			begin
				Next_SPSR=in_MEMSPSR2WB;
			end
			else
			begin
				//come direct from register without forward
				Next_SPSR=in_ALUSPSRReadBus;
			end

			Next_TargetRegister=in_ALUTargetRegister;
			
			Next_SimpleALUType=in_SimpleALUType;
			Next_SimpleALUTargetRegister=in_SimpleALUTargetRegister;

			Next_MEMType=in_MEMType;
			Next_MEMTargetRegister=in_MEMTargetRegister;
			Next_SimpleMEMType=in_SimpleMEMType;
			Next_SimpleMEMTargetRegister=in_SimpleMEMTargetRegister;
			
			//pass psr operation type to next stage mem
			Next_ALUPSRType=in_ALUPSRType;
			Next_MEMPSRType=in_MEMPSRType;
			
			Next_InstructionCondition=in_ALUMisc[31:28];
			
			Next_NextAddressGoWithInstruction2ALU=in_NextAddressGoWithInstruction2ALU;
			
			Next_IsBranch=in_ALUMisc[6];
			
			Next_IsLoadToPC=in_ALUMisc[7];
			
			Next_ALUOwnCanGo=1'b1;
			
			Next_IfChangeState=in_ALUMisc[8];
			Next_ChangeStateAction=in_ALUMisc[13:9];
			
			Next_MEMStoreDelayBranchTarget=in_ALUMisc[15];
			Next_MEMDelayBranch=in_ALUMisc[14];
			
			Next_MemAccessUserBankRegister=in_ALUMisc[16];
		   end
		   else
		   begin
		   	//now there is forward from mem to next alu operation
		   	//decoder wait for one cycle to let that operation goto mem
		   	//when that operation wait in mem for his result
		   	//the pipeline will be stall and that next alu operation can not go in 
		   	//alu until mem got his result and forward to that alu operation
		   	//so make a blank in alu but do go on
			Next_Valid=1'b0;
			Next_ALUType=`ALUType_Null;
			Next_LeftOperand=`WordZero;
			Next_RightOperand=`WordZero;
			Next_RightShiftType=`Def_ShiftTypeZero;
			Next_RightShiftCount=`Def_ShiftCountZero;
			Next_RightShiftCountHighBits=3'b000;
			Next_RightShiftCountInReg=1'b0;
			Next_Operand2IsReg=1'b0;
			Next_TargetRegister=`Def_LinkRegister;

			Next_CPSR=`WordZero;
			Next_SPSR=`WordZero;
			Next_StoredValue=`WordZero;
			
			Next_SimpleALUType=`ALUType_Null;
			Next_SimpleALUTargetRegister=`Def_LinkRegister;

			Next_MEMType=`MEMType_Null;
			Next_MEMTargetRegister=`Def_LinkRegister;
			Next_SimpleMEMType=`MEMType_Null;
			Next_SimpleMEMTargetRegister=`Def_LinkRegister;

			Next_ALUPSRType=`ALUPSRType_Null;
			Next_MEMPSRType=`MEMPSRType_Null;
			
			Next_InstructionCondition=`ConditionField_NV;
			Next_NextAddressGoWithInstruction2ALU=`AddressBusZero;
			
			Next_IsBranch=1'b0;
			
			Next_IsLoadToPC=1'b0;
			
			Next_ALUOwnCanGo=1'b0;

			Next_IfChangeState=1'b0;
			Next_ChangeStateAction=5'b00000;