alushell.v

若干VHDL语言的源代码

//////////////////////////////////////////////////////////////////
//		alu module definition				//
//////////////////////////////////////////////////////////////////
`include "Def_ALUType.v"
`include "Def_RegisterFile.v"
//`include "Def_ComponentEntry.v"
`include "Def_StructureParameter.v"
`include "Def_ConditionField.v"
`include "Def_BarrelShift.v"
`include "Def_mem.v"
`include "Def_psr.v"

module ALUShell(out_ALUWriteEnable,
		out_ALUWriteBus,		//write result
		out_CPSR,
		out_SPSR,
		out_ALUTargetRegister,	//write to which register
		out_SimpleALUResult,
		out_SimpleALUTargetRegister,
		out_MEMType,
		out_MEMTargetRegister,
		out_SimpleMEMType,
		out_SimpleMEMTargetRegister,
		out_StoredValue,
		out_ALUPSRType,
		out_MEMPSRType,
		out_IsLoadToPC,
		out_IfChangeState,
		out_ChangeStateAction,
		out_MEMStoreDelayBranchTarget,
		out_MEMDelayBranch,
		out_MemAccessUserBankRegister,
		//above is signal relate to write
		//below is signal relate to new operation
		in_ALUEnable,
		in_ALUType,
		in_ALULeftRegister,		
		in_ALURightRegister,		
		in_ALUThirdRegister,
		in_ALULeftFromImm,
		in_ALURightFromImm,
		in_ALUThirdFromImm,
		in_CPSRFromImm,
		in_SPSRFromImm,
		in_ALURightShiftType,
		in_ALULeftReadBus,
		in_ALURightReadBus,
		in_ALUThirdReadBus,
		in_ALUCPSRReadBus,
		in_ALUSPSRReadBus,
		in_ALUTargetRegister,
		in_SimpleALUType,
		in_SimpleALUTargetRegister,
		in_ALUMisc,
		in_ALUPSRType,
		in_NextAddressGoWithInstruction2ALU,
		//pass to mem stage for this instruction's mem operation
		in_MEMEnable,
		in_MEMType,
		in_MEMTargetRegister,
		in_SimpleMEMType,
		in_SimpleMEMTargetRegister,
		in_MEMPSRType,
		//below is signal relate to forward operand from mem stage
		in_MEMWriteEnable,
		in_MEMWriteResult,
		in_MEMTargetRegister2WB,
		in_SimpleMEMResult,
		in_SimpleMEMTargetRegister2WB,
		in_MEMPSRType2WB,
		in_MEMCPSR2WB,
		in_MEMSPSR2WB,
		//below is signal relate to ALUComb connection
		ALUCombResult,
		in_Carry,
		in_Zero,
		in_Neg,
		in_Overflow,
		ALUComb_ALUType,
		ALUComb_LeftOperand,
		ALUComb_RightOperand,
		ALUComb_ThirdOperand,
		ALUComb_RightOperandShiftType,
		ALUComb_RightOperandShiftCount,
		ALUComb_ShiftCountInReg,	//shift count in register
		ALUComb_ShiftCountHigh3Bit,	//the [7:5] bit of shoft count when shift count is in register
		ALUComb_Operand2IsReg,
		//origin CPSR flag
		ALUComb_Carry,
		ALUComb_Neg,
		ALUComb_Overflow,
		ALUComb_Zero,
		//signal relate to pc change in branch instruction
		out_ChangePC,
		out_NewPC,
		//can alu go
		out_ALUOwnCanGo,
		//can mem go
		in_MEMCanGo,
		//mem tell you to clear next operation
		in_MEMChangePC,
		//thumb state
		in_ThumbState,
		clock,
		reset
		);

//////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////
//		input and output declaration			//
//////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////
//signal for write
output						out_ALUWriteEnable;
output	[`WordWidth-1:0]			out_ALUWriteBus;
output	[`WordWidth-1:0]			out_CPSR,out_SPSR;
output	[`Def_RegisterSelectWidth-1:0]		out_ALUTargetRegister;
output	[`WordWidth-1:0]			out_SimpleALUResult;
output	[`Def_RegisterSelectWidth-1:0]	out_SimpleALUTargetRegister;
output	[`ByteWidth-1:0] 			out_MEMType;
output	[`Def_RegisterSelectWidth-1:0]	out_MEMTargetRegister;
output	[`ByteWidth-1:0]	out_SimpleMEMType;
output	[`Def_RegisterSelectWidth-1:0]		out_SimpleMEMTargetRegister;
output	[`WordWidth-1:0]			out_StoredValue;
output	[`ByteWidth-1:0]			out_ALUPSRType,
						out_MEMPSRType;
						
output						out_IsLoadToPC;

output						out_IfChangeState;
output	[4:0]					out_ChangeStateAction;

output						out_MEMStoreDelayBranchTarget,out_MEMDelayBranch;
output						out_MemAccessUserBankRegister;

reg						out_ALUWriteEnable;
reg	[`WordWidth-1:0]			out_CPSR,out_SPSR;


reg		[`WordWidth-1:0]			out_SimpleALUResult;
reg		[`Def_RegisterSelectWidth-1:0]	out_SimpleALUTargetRegister;


//signal for new operation
input							in_ALUEnable;
input	[`ByteWidth-1:0]				in_ALUType;
input	[`Def_RegisterSelectWidth-1:0]	in_ALULeftRegister,
							in_ALURightRegister,
							in_ALUThirdRegister;
input							in_ALULeftFromImm,
							in_ALURightFromImm,
							in_ALUThirdFromImm,
							in_CPSRFromImm,
							in_SPSRFromImm;
input	[`Def_ShiftTypeWidth-1:0]		in_ALURightShiftType;
input	[`WordWidth-1:0]				in_ALULeftReadBus,
							in_ALURightReadBus,
							in_ALUThirdReadBus;
input	[`WordWidth-1:0]				in_ALUCPSRReadBus,
							in_ALUSPSRReadBus;
							
input	[`Def_RegisterSelectWidth-1:0]	in_ALUTargetRegister;
input	[`ByteWidth-1:0]				in_SimpleALUType;
input	[`Def_RegisterSelectWidth-1:0]	in_SimpleALUTargetRegister;
input	[`WordWidth-1:0]		in_ALUMisc;
input	[`ByteWidth-1:0]		in_ALUPSRType;
input	[`AddressBusWidth-1:0]		in_NextAddressGoWithInstruction2ALU;

input in_MEMEnable;
input [`ByteWidth-1:0] in_MEMType;
input [`Def_RegisterSelectWidth-1:0] in_MEMTargetRegister;
input [`ByteWidth-1:0] in_SimpleMEMType;
input [`Def_RegisterSelectWidth-1:0] in_SimpleMEMTargetRegister;
input [`ByteWidth-1:0]			in_MEMPSRType;

//signal from mem
input							in_MEMWriteEnable;
input	[`WordWidth-1:0]				in_MEMWriteResult;
input	[`Def_RegisterSelectWidth-1:0]	in_MEMTargetRegister2WB;
input	[`ByteWidth-1:0]				in_MEMPSRType2WB;
input	[`WordWidth-1:0]				in_MEMCPSR2WB,
							in_MEMSPSR2WB;

input	[`WordWidth-1:0]				in_SimpleMEMResult;
input	[`Def_RegisterSelectWidth-1:0]	in_SimpleMEMTargetRegister2WB;

//signal for ALUComb connection
input	[`WordWidth-1:0]				ALUCombResult;
input							in_Carry,
							in_Zero,
							in_Neg,
							in_Overflow;
output	[`ByteWidth-1:0]			ALUComb_ALUType;
output	[`WordWidth-1:0]			ALUComb_LeftOperand,
							ALUComb_RightOperand,
							ALUComb_ThirdOperand;
output	[`Def_ShiftTypeWidth-1:0]	ALUComb_RightOperandShiftType;
output	[`Def_ShiftCountWidth-1:0]	ALUComb_RightOperandShiftCount;
output					ALUComb_ShiftCountInReg;
output	[2:0]				ALUComb_ShiftCountHigh3Bit;
output					ALUComb_Operand2IsReg;
output					ALUComb_Carry,ALUComb_Zero,ALUComb_Neg,ALUComb_Overflow;

//signal relate to change pc in branch instruction
output					out_ChangePC;
output	[`AddressBusWidth-1:0]		out_NewPC;
reg					out_ChangePC;
reg	[`AddressBusWidth-1:0]		out_NewPC;



//can alu go?
output						out_ALUOwnCanGo;

//can mem go?
input							in_MEMCanGo;

input							in_MEMChangePC;

input							in_ThumbState;

input							clock,
							reset;
//////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////
//		the register of pipeline			//
//////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////
//this means current instruction in alu is valid instruction and not a blank, 
//but this do not means it can live further, if it do not satisfy the condition field, 
//then it will not generate any thing to following stage
//and the out_ALUWriteEnable is the real flag that indicate  if current instruction in alu can live further
//only when an instruction is valid and it can satisfy the condition field, thus it can run to following stage
reg							Valid;	
reg	[`ByteWidth-1:0]				ALUType;
reg	[`WordWidth-1:0]				LeftOperand,
							RightOperand;
reg	[`Def_ShiftTypeWidth-1:0]		RightShiftType;
reg	[`Def_ShiftCountWidth-1:0]		RightShiftCount;
reg	[2:0]					RightShiftCountHighBits;
reg						RightShiftCountInReg;
reg						Operand2IsReg;
reg	[`Def_RegisterSelectWidth-1:0]	TargetRegister;

reg	[`ByteWidth-1:0]				SimpleALUType;
reg	[`Def_RegisterSelectWidth-1:0]	SimpleALUTargetRegister;

reg	[`ByteWidth-1:0]				MEMType;
reg	[`Def_RegisterSelectWidth-1:0]	MEMTargetRegister;
reg	[`ByteWidth-1:0]				SimpleMEMType;
reg	[`Def_RegisterSelectWidth-1:0]	SimpleMEMTargetRegister;
reg	[`WordWidth-1:0]		StoredValue;
reg	[`WordWidth-1:0]		CPSR,SPSR;
reg	[`ByteWidth-1:0]		ALUPSRType;
reg	[`ByteWidth-1:0]		MEMPSRType;
//in what condition can this instruction continue to run
reg	[3:0]				InstructionCondition;
reg	[`AddressBusWidth-1:0]		NextAddressGoWithInstruction2ALU;
reg					IsBranch;
reg					IsLoadToPC;
reg					ALUOwnCanGo;
//state change
reg					IfChangeState;
reg	[4:0]				ChangeStateAction;

//use in delay branch
reg					MEMStoreDelayBranchTarget,MEMDelayBranch;

//access user bank
reg					MemAccessUserBankRegister;


reg							Next_Valid;

reg	[`ByteWidth-1:0]				Next_ALUType;
reg	[`WordWidth-1:0]				Next_LeftOperand,
							Next_RightOperand;
reg	[`Def_ShiftTypeWidth-1:0]		Next_RightShiftType;
reg	[`Def_ShiftCountWidth-1:0]		Next_RightShiftCount;
reg	[2:0]					Next_RightShiftCountHighBits;
reg						Next_RightShiftCountInReg;
reg						Next_Operand2IsReg;
reg	[`Def_RegisterSelectWidth-1:0]	Next_TargetRegister;

reg	[`ByteWidth-1:0]				Next_SimpleALUType;
reg	[`Def_RegisterSelectWidth-1:0]	Next_SimpleALUTargetRegister;

reg	[`ByteWidth-1:0]				Next_MEMType;
reg	[`Def_RegisterSelectWidth-1:0]	Next_MEMTargetRegister;
reg	[`ByteWidth-1:0]				Next_SimpleMEMType;
reg	[`Def_RegisterSelectWidth-1:0]	Next_SimpleMEMTargetRegister;
reg	[`WordWidth-1:0]		Next_StoredValue;
reg	[`WordWidth-1:0]		Next_CPSR,Next_SPSR;
reg	[`ByteWidth-1:0]		Next_ALUPSRType;
reg	[`ByteWidth-1:0]		Next_MEMPSRType;
reg	[3:0]				Next_InstructionCondition;
reg	[`AddressBusWidth-1:0]		Next_NextAddressGoWithInstruction2ALU;
reg					Next_IsBranch;
reg					Next_IsLoadToPC;
reg					Next_ALUOwnCanGo;
//state change
reg					Next_IfChangeState;
reg	[4:0]				Next_ChangeStateAction;

reg					Next_MEMStoreDelayBranchTarget,Next_MEMDelayBranch;

//access user bank
reg					Next_MemAccessUserBankRegister;

//determine the current state of pipeline register
always @(posedge clock or negedge reset)
begin
	if(reset==1'b0)
	begin
		ALUType=`ALUType_Null;
		LeftOperand=`WordZero;
		RightOperand=`WordZero;
		RightShiftType=`Def_ShiftTypeZero;
		RightShiftCount=`Def_ShiftCountZero;
		RightShiftCountHighBits=3'b000;
		RightShiftCountInReg=1'b0;
		Operand2IsReg=1'b0;
		TargetRegister=`Def_LinkRegister;

		SimpleALUType=`ALUType_Null;
		SimpleALUTargetRegister=`Def_LinkRegister;

		MEMType=`MEMType_Null;
		MEMTargetRegister=`Def_LinkRegister;
		SimpleMEMType=`MEMType_Null;
		SimpleMEMTargetRegister=`Def_LinkRegister;
		
		StoredValue=`WordZero;
		
		CPSR=`WordZero;
		SPSR=`WordZero;
		ALUPSRType=`ALUPSRType_Null;
		MEMPSRType=`MEMPSRType_Null;
		
		InstructionCondition=`ConditionField_NV;
		
		NextAddressGoWithInstruction2ALU=`AddressBusZero;
		
		IsBranch=1'b0;
		
		IsLoadToPC=1'b0;
		
		Valid=1'b0;
		
		ALUOwnCanGo=1'b1;
		
		IfChangeState=1'b0;
		ChangeStateAction=5'b00000;
		
		//delay branch signal
		MEMStoreDelayBranchTarget=1'b0;
		MEMDelayBranch=1'b0;
		
		MemAccessUserBankRegister=1'b0;
	end
	else
	begin
		ALUType=Next_ALUType;
		LeftOperand=Next_LeftOperand;
		RightOperand=Next_RightOperand;
		RightShiftType=Next_RightShiftType;
		RightShiftCount=Next_RightShiftCount;
		RightShiftCountHighBits=Next_RightShiftCountHighBits;
		RightShiftCountInReg=Next_RightShiftCountInReg;
		Operand2IsReg=Next_Operand2IsReg;

		TargetRegister=Next_TargetRegister;

		SimpleALUType=Next_SimpleALUType;
		SimpleALUTargetRegister=Next_SimpleALUTargetRegister;

		MEMType=Next_MEMType;
		MEMTargetRegister=Next_MEMTargetRegister;
		SimpleMEMType=Next_SimpleMEMType;
		SimpleMEMTargetRegister=Next_SimpleMEMTargetRegister;

		StoredValue=Next_StoredValue;
		
		CPSR=Next_CPSR;
		SPSR=Next_SPSR;
		ALUPSRType=Next_ALUPSRType;
		MEMPSRType=Next_MEMPSRType;
		
		InstructionCondition=Next_InstructionCondition;

		NextAddressGoWithInstruction2ALU=Next_NextAddressGoWithInstruction2ALU;
		
		IsBranch=Next_IsBranch;