nnarmcore.v

若干VHDL语言的源代码

`include "Def_StructureParameter.v"
`include "IF.v"
`include "Decoder_ARM.v"
`include "ALUShell.v"
`include "ALUComb.v"
`include "mem.v"
`include "RegisterFile.v"
`include "CanGoGen.v"
`include "psr.v"
`include "ThumbDecoderWarper.v"
`include "InterruptPriority.v"
`include "PSR_Fresh.v"

module nnARMCore(//signal between bus2core and IF
		Wait,			//if fetch ready?
		Instruction,		//fetch back instruction
		out_InstructionAddress,	//send out fetch address
		//signal between mem and DataCacheController
		out_MEMAccessAddress,		//data address go to data cache
		DataBus_r,		//data value for read of memory
		DataBus_f,		//data value write to memory
		out_MEMAccessRequest,	//enable access to data cache
		out_MEMAccessBW,			//1 means byte,0 means word
		out_MEMAccessRW,			//1 means read,0 means write
		out_DataCacheWait,		//wait signal come from data cache
		//interrupt signal
		Fiq,
		Irq,
		clock,
		reset);

//these signal will never be use anymore
//the signal between instruction cache and instruction prefetch
//input [`InstructionCacheLineWidth-1:0] InstructionOut;
//input InstructionWait;
//output [`AddressBusWidth-1:0] PreFetchedAddress;
//output PreFetchedRequest;

//signal between mem and data cache
output	[`AddressBusWidth-1:0]		out_MEMAccessAddress;
output					out_MEMAccessRequest,
					out_MEMAccessRW,
					out_MEMAccessBW;
input					out_DataCacheWait;

input	[`WordWidth-1:0]		DataBus_r;
output	[`WordWidth-1:0]		DataBus_f;




input	Fiq,Irq;

//global signal 
input clock,reset;

input Wait;
input [`InstructionWidth-1:0] Instruction;
output	[`AddressBusWidth-1:0] out_InstructionAddress;


wire	[`AddressBusWidth-1:0] out_NextInstructionAddress;

//signal between if and register file
//use to update pc and read pc
wire		out_FourthReadRegisterEnable;
wire	[`Def_RegisterSelectWidth-1:0]	out_FourthReadRegisterNumber;
wire	[`WordWidth-1:0] FourthReadBus;
wire		out_SecondWriteRegisterEnable;
wire	[`Def_RegisterSelectWidth-1:0]	out_SecondWriteRegisterNumber;
//wire	[`WordWidth-1:0]	SecondWriteBus;

//signal between if and id
wire  [`InstructionWidth-1:0]	Pipeline_IFID;
wire					Valid_Pipeline_IFID;
wire	[`AddressBusWidth-1:0]	out_AddressGoWithInstruction;

//signal between id and register file
wire	out_LeftReadRegisterEnable,out_RightReadRegisterEnable,out_ThirdReadRegisterEnable;
wire	[`Def_RegisterSelectWidth-1:0]	out_LeftReadRegisterNumber,out_RightReadRegisterNumber,out_ThirdReadRegisterNumber;

//signal from Thumb decoder to arm decoder
wire	out_NewA1;
wire	[`InstructionWidth-1:0]	out_nnARMInstruction;
wire	[`AddressBusWidth-1:0]	out_NewAddressGoWithInstruction;

//signal between decoder and alu
wire out_ALUEnable;
wire [`ByteWidth-1:0] out_ALUType;
wire [`Def_RegisterSelectWidth-1:0] out_ALULeftRegister;
wire [`Def_RegisterSelectWidth-1:0] out_ALURightRegister;
wire [`Def_RegisterSelectWidth-1:0] out_ALUThirdRegister;
wire out_ALULeftFromImm;
wire out_ALURightFromImm;
wire out_ALUThirdFromImm;
wire out_CPSRFromImm;
wire out_SPSRFromImm;
wire [`Def_RegisterSelectWidth-1:0] out_ALUTargetRegister;
wire [`Def_ShiftTypeWidth-1:0] out_ALURightShiftType;
wire [`ByteWidth-1:0]	out_SimpleALUType;
wire [`Def_RegisterSelectWidth-1:0]	out_SimpleALUTargetRegister;
wire [`WordWidth-1:0]			out_ALUMisc;
wire [`ByteWidth-1:0]			out_ALUPSRType;
wire [`AddressBusWidth-1:0]		out_NextAddressGoWithInstruction2ALU;

//signal bwtween decoder and mem
wire			out_MEMEnable;
wire [`ByteWidth-1:0]	out_MEMType;
wire [`Def_RegisterSelectWidth-1:0]	out_MEMTargetRegister;
wire [`ByteWidth-1:0]	out_SimpleMEMType;
wire [`Def_RegisterSelectWidth-1:0]	out_SimpleMEMTargetRegister;
wire [`ByteWidth-1:0]			out_MEMPSRType;

//signal go from alu to mem
wire	out_ALUWriteEnable;
wire	[`WordWidth-1:0]  out_ALUWriteBus;
wire	[`WordWidth-1:0]	out_ALUCPSR2MEM,out_ALUSPSR2MEM;
wire	[`Def_RegisterSelectWidth-1:0] out_ALUTargetRegister2MEM;
wire	[`WordWidth-1:0]			out_SimpleALUResult2MEM;
wire	[`Def_RegisterSelectWidth-1:0]	out_SimpleALUTargetRegister2MEM;
wire	[`ByteWidth-1:0]			out_MEMType2MEM;
wire	[`Def_RegisterSelectWidth-1:0]			out_MEMTargetRegister2MEM;
wire	[`ByteWidth-1:0]			out_SimpleMEMType2MEM;
wire	[`Def_RegisterSelectWidth-1:0]			out_SimpleMEMTargetRegister2MEM;
wire	[`WordWidth-1:0]				out_StoredValue;
wire	[`ByteWidth-1:0]				out_MEMPSRType2MEM,out_ALUPSRType2MEM;
wire						out_IsLoadToPC;
wire						out_IfChangeState2MEM;
wire	[4:0]					out_ChangeStateAction2MEM;
wire						out_MEMStoreDelayBranchTarget2MEM,out_MEMDelayBranch2MEM;
wire						out_MemAccessUserBankRegister2MEM;

//signal go out of mem and into wb and forward to alu
wire			out_MEMWriteEnable;
wire	[`WordWidth-1:0]	out_MEMWriteResult;
wire	[`Def_RegisterSelectWidth-1:0]	out_MEMTargetRegister2WB;
wire	[`WordWidth-1:0]			out_SimpleMEMResult2WB;
wire	[`Def_RegisterSelectWidth-1:0]	out_SimpleMEMTargetRegister2WB;
wire	[`ByteWidth-1:0]		out_MEMPSRType2WB;
wire	[`WordWidth-1:0]		out_CPSR2WB,out_SPSR2WB;

//connection between ALUShell and ALUComb
wire	[`WordWidth-1:0]	ALUCombResult;
wire			Carry,Zero,Neg,Overflow;
wire	[`ByteWidth-1:0]	ALUComb_ALUType;
wire	[`WordWidth-1:0]	ALUComb_LeftOperand,
			ALUComb_RightOperand,
			ALUComb_ThirdOperand;
wire	[`Def_ShiftTypeWidth-1:0]	ALUComb_RightOperandShiftType;
wire	[`Def_ShiftCountWidth-1:0]	ALUComb_RightOperandShiftCount;
wire	[2:0]				ALUComb_ShiftCountHigh3Bit;
wire					ALUComb_ShiftCountInReg;
wire					ALUComb_Operand2IsReg;
wire					ALUComb_Carry,ALUComb_Neg,ALUComb_Zero,ALUComb_Overflow;

//who can go and who can not go
wire	out_IFCanGo,out_IFOwnCanGo;
wire	out_IDCanGo,out_IDOwnCanGo;
wire	out_EXECanGo,out_EXEOwnCanGo;
wire	out_MEMCanGo,out_MEMOwnCanGo;

//psr register file
wire	[`WordWidth-1:0]		out_CPSR,out_SPSR;
wire					in_SPSRWriteEnable;
wire					in_CPSRWriteEnable;
wire	[`WordWidth-1:0]		out_CPSRWriteValue,out_SPSRWriteValue;
wire	[4:0]				out_ChangeStateAction2WB;
wire					out_IfChangeState2WB;
wire					out_MemAccessUserBankRegister2WB;

//alu send out these signal to if to update pc
wire					out_ChangePC;
wire	[`AddressBusWidth-1:0]		out_NewPC;

//mem send out these signal to if to update pc
wire					out_MEMChangePC;
wire	[`AddressBusWidth-1:0]		out_MEMNewPC;

//fresh cpsr
wire	[`WordWidth-1:0]		out_CPSR_Fresh;
wire					out_IsInPrivilegedMode;

//global signal
wire [`WordWidth-1:0] LeftReadBus,RightReadBus,ThirdReadBus,WriteBus,SecondWriteBus,ThirdWriteBus;
wire	[`WordWidth-1:0]	mux_LeftReadBus,dec_LeftReadBus,reg_LeftReadBus;
wire	[`WordWidth-1:0]	mux_RightReadBus,dec_RightReadBus,reg_RightReadBus;
wire	[`WordWidth-1:0]	mux_ThirdReadBus,dec_ThirdReadBus,reg_ThirdReadBus;

wire WriteRegisterEnable,ThirdWriteRegisterEnable;
wire [`Def_RegisterSelectWidth-1:0] WriteRegisterNumber,ThirdWriteRegisterNumber;

//wire between decoder and InterruptPriority
wire	TrueFiq,TrueIrq;

PSR_Fresh		inst_PSR_Fresh(	//varies CPSR input
			.in_CPSR_StatusRegisters(out_CPSR),	//cpsr come from StatusRegisters
			.in_CPSR_ALUShell(out_ALUCPSR2MEM),	//CPSR come from ALUShell stage
			.in_ALUWriteEnable(out_ALUWriteEnable),	// if current alu have valid output
			.in_CPSR_MEM(out_CPSR2WB),		//cpsr come from MEM stage
			.in_MEMWriteEnable(out_MEMWriteEnable),	//if current mem have valid output
		
			//output of fresh cpsr
			.out_CPSR_Fresh(out_CPSR_Fresh),
			.out_IsInPrivilegedMode(out_IsInPrivilegedMode)
);

InterruptPriority	inst_InterruptPriority(//interrupt signal
			.Fiq(Fiq),
			.Irq(Irq),
			//interrupt mask
			.FiqDisable(out_CPSR_Fresh[`FiqPos]),
			.IrqDisable(out_CPSR_Fresh[`IrqPos]),
			//output interrupt signal
			.TrueFiq(TrueFiq),
			.TrueIrq(TrueIrq)
			);

CanGoGen		inst_CanGoGen(.out_IFCanGo(out_IFCanGo),
					.out_IDCanGo(out_IDCanGo),
					.out_EXECanGo(out_EXECanGo),
					.out_MEMCanGo(out_MEMCanGo),
					.in_IFOwnCanGo(out_IFOwnCanGo),
					.in_IDOwnCanGo(out_IDOwnCanGo),
					.in_EXEOwnCanGo(out_EXEOwnCanGo),
					.in_MEMOwnCanGo(out_MEMOwnCanGo)
);

StatusRegisters		inst_StatusRegisters(	//change of state
			.in_IfChangeState(out_IfChangeState2WB),
			.in_ChangeStateAction(out_ChangeStateAction2WB),
			//write to register
			.in_CPSRWriteEnable(out_CPSRWriteEnable),
			.in_CPSRWriteValue(out_CPSRWriteValue),
			.in_SPSRWriteEnable(out_SPSRWriteEnable),
			.in_SPSRWriteValue(out_SPSRWriteValue),
			//output of status register
			.out_CPSR(out_CPSR),
			.out_SPSR(out_SPSR),
			.clock(clock),
			.reset(reset)
);


RegisterFile  inst_RegisterFile(	//change of state
			.in_IfChangeState(out_IfChangeState2WB),
			.in_MemAccessUserBankRegister2WB(out_MemAccessUserBankRegister2WB),
			.in_ChangeStateAction(out_ChangeStateAction2WB),
			.in_LeftReadEnable(out_LeftReadRegisterEnable),
			.in_LeftReadRegisterNumber(out_LeftReadRegisterNumber),
			.out_LeftReadBus(reg_LeftReadBus),
			.in_RightReadEnable(out_RightReadRegisterEnable),
			.in_RightReadRegisterNumber(out_RightReadRegisterNumber),
			.out_RightReadBus(reg_RightReadBus),
			.in_ThirdReadEnable(out_ThirdReadRegisterEnable),
			.in_ThirdReadRegisterNumber(out_ThirdReadRegisterNumber),
			.out_ThirdReadBus(reg_ThirdReadBus),
			.in_FourthReadEnable(out_FourthReadRegisterEnable),
			.in_FourthReadRegisterNumber(out_FourthReadRegisterNumber),
			.out_FourthReadBus(FourthReadBus),
			.in_WriteEnable(WriteRegisterEnable),
			.in_WriteRegisterNumber(WriteRegisterNumber),
			.in_WriteBus(WriteBus),
			.in_SecondWriteEnable(out_SecondWriteRegisterEnable),
			.in_SecondWriteRegisterNumber(out_SecondWriteRegisterNumber),
			.in_SecondWriteBus(SecondWriteBus),
			.in_ThirdWriteEnable(ThirdWriteRegisterEnable),
			.in_ThirdWriteRegisterNumber(ThirdWriteRegisterNumber),
			.in_ThirdWriteBus(ThirdWriteBus),
			//the processor mode
			.in_ProcessorMode(out_CPSR[4:0]),
			.clock(clock),
			.reset(reset)
);

//WB	inst_WB(//the write to register file
//		.out_WBWriteBus(WriteBus),
//		.out_WBWriteEnable(WriteRegisterEnable),
//		.out_WBWriteTargetRegister(WriteRegisterNumber),
		//input from mem
//		.in_MEMWriteEnable(out_MEMWriteEnable),
//		.in_MEMWriteResult(out_MEMWriteResult),
//		.in_MEMWriteTargetRegister(out_MEMTargetRegister),
//		.clock(clock),
//		.reset(reset)
//		);


MEM	inst_MEM(	//signal from ALU
			.in_ALUValid(out_ALUWriteEnable),
			.in_ALUWriteBus(out_ALUWriteBus),
			.in_ALUTargetRegister(out_ALUTargetRegister2MEM),
			.in_SimpleALUResult(out_SimpleALUResult2MEM),
			.in_SimpleALUTargetRegister(out_SimpleALUTargetRegister2MEM),
			.in_StoredValue(out_StoredValue),
			.in_CPSR(out_ALUCPSR2MEM),