readme.txt

若干VHDL语言的源代码

-------------------- synthsis files -----------------------------------------

Adder.v		contain WordAdder module that add two 32bit word together

ALUComb.v	The combinatinal logic module ALUComb perform varies ALU operation auch as Add , Or , Not. this module  is mounted on ALUShell with is part of nnARM pipeline

ALUShell.v	ALUShell module is the EXE stage of pipeline

BarrelShifter.v	BarrelShifter is instance in ALUComb to perform varies type of shift operation

CanGoGen.v	CanGoGen module perform pipeline interlock signal generation

complementory.v	generate complementory value of B and put it to adder when perform A-B operation in ALUComb module

DataCacheContaoller.v	this is the behavior level description of data cache.

Decoder_ARM	Decoder_ARM module is the decode stage of pipeline

IF.v		instruction fetch stage of pipeline

InstructionCacheController.v	behavior decription of instruction cache

InstructionPrefetch.v	Instruction prefetch stage of pipeline

mem.v		MEM stage of pipeline

MemoryController.v	the behavior description of memory

mul.v		a function to perform 32 bit multiple

nnARMCore.v	top level synthesis module of nnARM, it contain all nnARM component

psr.v		CPSR and SPSR register

RegisterFile.v	3 read and 2 write register file

Thumb_2_nnARM.v	translate Thumb code to nnARM instruction

ThumbDecoderWarper.v	pack Thumb_2_nnARM and the switchs to form a new module

InterruptPriority.v	decide if varies interrupt can generate

PSR_Fresh.v	use to generate the most fresh version of CPSR from within pipeline, because some pipeline stage may change CPSR value

---------------------- simulation files --------------------------------------------------------------
nnARM.prog	this file is a record about the development of nnARM, it is in Chinese plain text

nnARM1.v	interconnect nnARMCore module with cache and memory, this is only use to simulate nnARM, no use in synthesis

tb_system.v	top level simulate module

timescalar.v	simulation time unit

-----------------------file define something use both in synthesis and simulate---------------------
Def_XXXX.v