mem.v

若干VHDL语言的源代码

	   	//mem can go
		//exe can not go
		//make a blank in mem
		Next_Valid=1'b0;
		Next_MEMType=`MEMType_Null;
		Next_SimpleMEMType=`MEMType_Null;
		Next_ALUResult=`WordZero;
		Next_SimpleALUResult=`WordZero;
		Next_MEMTargetRegister=`Def_LinkRegister;
		Next_SimpleMEMTargetRegister=`Def_LinkRegister;
		Next_StoredValue=`WordZero;
		Next_MEMPSRType=`MEMPSRType_Null;
		Next_CPSR=`WordZero;
		Next_SPSR=`WordZero;
		Next_IsLoadToPC=1'b0;
		Next_IfChangeState=1'b0;
		Next_ChangeStateAction=5'b00000;
		Next_MEMStoreDelayBranchTarget=1'b0;
		Next_MEMDelayBranch=1'b0;
		Next_MemAccessUserBankRegister2MEM=1'b0;
	   end
	end
	else
	begin
		//mem can not go 
		//save current value of register that come from outside
		//all state register that relate to memory access will not be write here
		Next_Valid=Valid;
		Next_MEMType=MEMType;
		Next_SimpleMEMType=SimpleMEMType;
		Next_ALUResult=ALUResult;
		Next_SimpleALUResult=SimpleALUResult;
		Next_MEMTargetRegister=MEMTargetRegister;
		Next_SimpleMEMTargetRegister=SimpleMEMTargetRegister;
		Next_StoredValue=StoredValue;
		Next_MEMPSRType=MEMPSRType;
		Next_CPSR=CPSR;
		Next_SPSR=SPSR;
		Next_IsLoadToPC=IsLoadToPC;
		Next_IfChangeState=IfChangeState;
		Next_ChangeStateAction=ChangeStateAction;
		Next_MEMStoreDelayBranchTarget=MEMStoreDelayBranchTarget;
		Next_MEMDelayBranch=MEMDelayBranch;
		Next_MemAccessUserBankRegister2MEM=MemAccessUserBankRegister2MEM;
	end
end

//simple thread
always @(SimpleMEMType or
		ALUResult or
		SimpleALUResult or
		SimpleMEMTargetRegister	or
		out_MEMOwnCanGo	or
		out_SimpleMEMResult or
		out_SimpleMEMTargetRegister
)
begin
	case (SimpleMEMType)
	`MEMType_MovMain:
		out_SimpleMEMResult=ALUResult;
	`MEMType_MovSimple:
		out_SimpleMEMResult=SimpleALUResult;
	default:
		out_SimpleMEMResult=`WordZero;
	endcase
	//simple mem target register
	out_SimpleMEMTargetRegister=SimpleMEMTargetRegister;
	//write back register 
	if(out_MEMOwnCanGo==1'b1)
	begin
		out_ThirdWriteBus=out_SimpleMEMResult;
		out_ThirdWriteRegisterEnable=1'b1;
		out_ThirdWriteRegisterNumber=out_SimpleMEMTargetRegister;
	end
	else
	begin
		out_ThirdWriteBus=out_SimpleMEMResult;
		out_ThirdWriteRegisterEnable=1'b0;
		out_ThirdWriteRegisterNumber=out_SimpleMEMTargetRegister;
	end
end

//main thread
always @(MEMType or
		ALUResult or
		SimpleALUResult or
		MEMTargetRegister or
		in_DataCacheWait or
		in_DataBus	or
		StoredValue	or
		MEMStoreDelayBranchTarget	or
		MEMDelayBranch	or
		DelayBranchTarget
	)
begin
	//only use by load/store
	out_MEMAccessAddress=`AddressBusZ;
	out_MEMAccessRequest=1'b0;
	out_MEMAccessRW=1'b1;
	out_MEMAccessBW=1'b0;
	tmp_DataBus=`WordDontCare;
	//can not output to data bus
	//only store can make it be 1
	CanOutputToDataBus=1'b0;
	
	//delay branch target
	if(MEMDelayBranch==1'b1)
		Next_DelayBranchTarget=`WordZero;
	else
		Next_DelayBranchTarget=DelayBranchTarget;

	case (MEMType)
	`MEMType_MovMain:
	begin
		out_MEMWriteResult=ALUResult;
		out_MEMOwnCanGo=1'b1;
		if(MEMTargetRegister!=`Def_LinkRegister)
		begin
			out_WriteBus=ALUResult;
			out_WriteRegisterEnable=1'b1;
			out_WriteRegisterNumber=MEMTargetRegister;
		end
		else
		begin
			out_WriteBus=ALUResult;
			out_WriteRegisterEnable=1'b0;
			out_WriteRegisterNumber=MEMTargetRegister;
		end
	end
	`MEMType_MovSimple:
	begin
		out_MEMWriteResult=SimpleALUResult;
		out_MEMOwnCanGo=1'b1;
		if(MEMTargetRegister!=`Def_LinkRegister)
		begin
			out_WriteBus=SimpleALUResult;
			out_WriteRegisterEnable=1'b1;
			out_WriteRegisterNumber=MEMTargetRegister;
		end
		else
		begin
			out_WriteBus=SimpleALUResult;
			out_WriteRegisterEnable=1'b0;
			out_WriteRegisterNumber=MEMTargetRegister;
		end
	end
	`MEMType_LoadMainWord,`MEMType_LoadMainByte,`MEMType_LoadSimpleWord,`MEMType_LoadSimpleByte:
	begin
			if(MEMType==`MEMType_LoadMainWord || MEMType==`MEMType_LoadMainByte)
			begin//load main
				out_MEMAccessAddress=ALUResult;
			end
			else//load simple
			begin
				out_MEMAccessAddress=SimpleALUResult;
			end
			out_MEMAccessRequest=1'b1;
			out_MEMAccessRW=1'b1;
			if(MEMType==`MEMType_LoadMainByte || MEMType==`MEMType_LoadSimpleByte)
			begin//byte
				out_MEMAccessBW=1'b1;
			end
			else//word
			begin
				out_MEMAccessBW=1'b0;
			end
			tmp_DataBus=`WordDontCare;

			if(in_DataCacheWait==1'b1)
			begin
				out_MEMWriteResult=`WordZero;
				out_MEMOwnCanGo=1'b0;
				//nothing writen to register
				out_WriteBus=`WordZero;
				out_WriteRegisterEnable=1'b0;
				out_WriteRegisterNumber=MEMTargetRegister;
			end
			else
			begin
				out_MEMWriteResult=in_DataBus;
				out_MEMOwnCanGo=1'b1;
				//nothing writen to register
				out_WriteBus=in_DataBus;
				out_WriteRegisterEnable=1'b1;
				out_WriteRegisterNumber=MEMTargetRegister;
				if(MEMStoreDelayBranchTarget==1'b1)
					Next_DelayBranchTarget=in_DataBus;
			end
	end
	`MEMType_StoreMainWord,`MEMType_StoreMainByte,`MEMType_StoreSimpleWord,`MEMType_StoreSimpleByte:
	begin
			//send out address
			if(MEMType==`MEMType_StoreMainWord || MEMType==`MEMType_StoreMainByte)
			begin//Store main
				out_MEMAccessAddress=ALUResult;
			end
			else//Store simple
			begin
				out_MEMAccessAddress=SimpleALUResult;
			end
			out_MEMAccessRequest=1'b1;
			out_MEMAccessRW=1'b0;
			if(MEMType==`MEMType_StoreMainByte || MEMType==`MEMType_StoreSimpleByte)
			begin//byte
				out_MEMAccessBW=1'b1;
			end
			else//word
			begin
				out_MEMAccessBW=1'b0;
			end
			//only store can write to data cache bus
			CanOutputToDataBus=1'b1;
			tmp_DataBus=StoredValue;

			if(in_DataCacheWait==1'b1)
			begin
				out_MEMWriteResult=`WordZero;
				out_MEMOwnCanGo=1'b0;

				out_WriteBus=`WordZero;
				out_WriteRegisterEnable=1'b0;
				out_WriteRegisterNumber=MEMTargetRegister;
			end
			else
			begin
				out_MEMWriteResult=`WordZero;
				out_MEMOwnCanGo=1'b1;

				out_WriteBus=`WordZero;
				out_WriteRegisterEnable=1'b0;
				out_WriteRegisterNumber=MEMTargetRegister;
			end
	end
	default:
	begin
		out_MEMWriteResult=`WordZero;
		out_MEMOwnCanGo=1'b1;
		if(MEMTargetRegister!=`Def_LinkRegister)
		begin
			out_WriteBus=ALUResult;
			out_WriteRegisterEnable=1'b0;
			out_WriteRegisterNumber=MEMTargetRegister;
		end
		else
		begin
			out_WriteBus=ALUResult;
			out_WriteRegisterEnable=1'b0;
			out_WriteRegisterNumber=MEMTargetRegister;
		end
	end
	endcase
	out_MEMTargetRegister=MEMTargetRegister;
end

assign	out_MEMWriteEnable=Valid;


//psr thread
always @(MEMPSRType or
	CPSR or
	SPSR
	)
begin
	out_MEMPSRType2WB=MEMPSRType;
	out_CPSR2WB=CPSR;
	out_SPSR2WB=SPSR;
	out_CPSR2PSR=CPSR;
	out_SPSR2PSR=SPSR;
	
	
	case (MEMPSRType)
	`MEMPSRType_WriteSPSR:
	begin
		out_CPSRWriteEnable=1'b0;
		out_SPSRWriteEnable=1'b1;
	end
	`MEMPSRType_SPSR2CPSR:
	begin
		out_CPSRWriteEnable=1'b1;
		out_SPSRWriteEnable=1'b0;
	end
	`MEMPSRType_WriteCPSR:
	begin
		out_CPSRWriteEnable=1'b1;
		out_SPSRWriteEnable=1'b0;
	end
	`MEMPSRType_WriteConditionCode:
	begin
		out_CPSRWriteEnable=1'b1;
		out_SPSRWriteEnable=1'b0;
	end
	`MEMPSRType_WriteBoth:
	begin
		out_CPSRWriteEnable=1'b1;
		out_SPSRWriteEnable=1'b1;
	end
	default:
	begin
		out_CPSRWriteEnable=1'b0;
		out_SPSRWriteEnable=1'b0;
	end
	endcase
end

//output to cache
assign	out_DataBus=tmp_DataBus;

assign	out_MemAccessUserBankRegister2WB=MemAccessUserBankRegister2MEM;
//the following two signal go to register file and psr registers
//so you can not modify them to use in LDM/STM
assign	out_IfChangeState=IfChangeState;
assign	out_ChangeStateAction=ChangeStateAction;

//can write pc?
always @(out_MEMWriteEnable	or
	IsLoadToPC		or
	out_MEMWriteResult	or
	MEMDelayBranch		or
	DelayBranchTarget
)
begin
	if(out_MEMWriteEnable==1'b1)
	begin
		if(IsLoadToPC==1'b1)
		begin
			//can write pc
			out_MEMChangePC=~in_DataCacheWait;
			out_MEMNewPC={out_MEMWriteResult[`WordWidth-1:2],out_CPSR2WB[`ThumbPos]&out_MEMWriteResult[1],1'b0};//half word align
		end
		else if(MEMDelayBranch==1'b1)
		begin
			//delay branch
			out_MEMChangePC=1'b1;
			out_MEMNewPC={DelayBranchTarget[`WordWidth-1:2],out_CPSR2WB[`ThumbPos]&DelayBranchTarget[1],1'b0};//half word align
		end
		else
		begin
			out_MEMChangePC=1'b0;
			out_MEMNewPC={out_MEMWriteResult[`WordWidth-1:2],out_CPSR2WB[`ThumbPos]&out_MEMWriteResult[1],1'b0};//half word align
		end
	end
	else
	begin
		out_MEMChangePC=1'b0;
		out_MEMNewPC={out_MEMWriteResult[`WordWidth-1:2],out_CPSR2WB[`ThumbPos]&out_MEMWriteResult[1],1'b0};//half word align
	end
end
endmodule