xllp_msl.c

Xcale270Bsp包,wince平台

/******************************************************************************
**
**  COPYRIGHT (C) 2000, 2002 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:       mslxllp.c
**
**  PURPOSE:        This is the main source file for the XLLP primitives for the 
**					Mobile Scalable Link (MSL) bus.
**
******************************************************************************/

#include "xllp_msl.h"

#define XLLP_CLEAR_BITS(origValue,bitsToClear)	(origValue) &= ~bitsToClear;
#define XLLP_SET_BITS(origValue,bitsToSet)		(origValue) |=  bitsToSet;


//******************************************************************************
// XLLP_DOC_HDR_BEGIN
//
// Function Name: XllpMslConfigureBus
//
// Description: 
//  
// Registers Modified: 
//
// Input Arguments:
//	                 
// Output Arguments:
//
// Return Value: 
//
// XLLP_DOC_HDR_END
//*******************************************************************************
void XllpMslConfigureBus
(		
	P_XllpMslRegT				pMslRegBase, 
	XLLP_UINT32_T				maxNumChannels,
	XllpMslInterfaceWidthTypeT	interfaceWidth, 	
	XLLP_UINT32_T				xmitFreqDivisor,
	XLLP_UINT32_T				clockStopTime,
	XLLP_UINT32_T				mfcStopThreshold,
	XLLP_UINT32_T				mfcStartThreshold,
    XLLP_UINT32_T               waitTime
)
{
	XLLP_UINT32_T				width;

	//
	// Set the interface width
	//
	width = (interfaceWidth << XLLP_MSL_BBITFC_RXITFC) | 
		    (interfaceWidth << XLLP_MSL_BBITFC_TXITFC);
	pMslRegBase->ControlReg.BBITFC = width;

	//
	// Update the MFC channel Start/Stop threshlds
	// The Receive channels need to be disabled when doing this
	//
	pMslRegBase->ControlReg.BBCSTP = mfcStopThreshold;
	pMslRegBase->ControlReg.BBCSTR = mfcStartThreshold;

	//
	// Clock Stop Time
	//
	pMslRegBase->ControlReg.BBCST = clockStopTime;
	
    //
    // Wait time
    //
    pMslRegBase->ControlReg.BBWAIT = waitTime;

	//
	// Set Transmit Frequency
	//
	pMslRegBase->ControlReg.BBFREQ = (xmitFreqDivisor << XLLP_MSL_BBFREQ_DIV);

	return;
}


void XllpMslEmptyRxFifo
(
	P_XllpMslRegT				pMslRegBase, 
	XLLP_INT32_T				channel
)
{
    XLLP_UINT32_T				status;
    XLLP_UINT32_T				data;
    XLLP_UINT32_T				maxDataCount=XLLP_MSL_MAX_RX_FIFO;
    
    
    while(maxDataCount--)
    {
        XllpMslGetChannelStatus (pMslRegBase, channel, &status);
	    if(status & XLLP_MSL_BBSTAT_RxEmpty)
		    break;
        data = pMslRegBase->FifoReg.BBFIFO[channel];
    }
	
}

void XllpMslConfigureRxChannel
(	
	P_XllpMslRegT				pMslRegBase, 
	XLLP_INT32_T				channel,
	XllpMslChannelEnableTypeT	rxChannelEnable,
	XllpMslMfcEnableTypeT		rxMfcEnable,
	XllpMslDfcEnableTypeT		rxDfcEnable,
	XllpMslFifoSvcThreshTypeT	fifoSvcThreshold,
	XllpMslFifoServiceTypeT		fifoServiceType,	
	XllpMslEocServiceTypeT		eocServiceType
)
{
	XLLP_UINT32_T				channelCfg;
	XLLP_UINT32_T				bitsToClear;
	XLLP_UINT32_T				bitsToSet;

	//
	// Set the specified receive configuration in BBCFG for the specified channel
	//

	channelCfg = pMslRegBase->ConfigReg.BBCFG[channel];

	bitsToClear= (0x1U << XLLP_MSL_BBCFG_RxEnable)			|
		         (0x1U << XLLP_MSL_BBCFG_RxMFCEnable)		|
				 (0x1U << XLLP_MSL_BBCFG_RxDFCEnable)		|
				 (0x3U << XLLP_MSL_BBCFG_RxThreshLevel)		|
				 (0x7U << XLLP_MSL_BBCFG_RxService)			|
				 (0x3U << XLLP_MSL_BBCFG_EOCService);


	bitsToSet  = (rxChannelEnable << XLLP_MSL_BBCFG_RxEnable)		|
		         (rxMfcEnable     << XLLP_MSL_BBCFG_RxMFCEnable)	|
				 (rxDfcEnable     << XLLP_MSL_BBCFG_RxDFCEnable)	|
				 (fifoSvcThreshold<< XLLP_MSL_BBCFG_RxThreshLevel)	|
				 (fifoServiceType << XLLP_MSL_BBCFG_RxService)		|
				 (eocServiceType  << XLLP_MSL_BBCFG_EOCService);


	XLLP_CLEAR_BITS(channelCfg, bitsToClear);
	XLLP_SET_BITS  (channelCfg, bitsToSet);
	
	pMslRegBase->ConfigReg.BBCFG[channel] = channelCfg;

	return;
}
						  
void XllpMslConfigureTxChannel
(
	P_XllpMslRegT				pMslRegBase,
	XLLP_INT32_T				channel,
	XllpMslChannelEnableTypeT	txChannelEnable,
	XllpMslMfcEnableTypeT		txMfcEnable,
	XllpMslDfcEnableTypeT		txDfcEnable,
	XllpMslFifoSvcThreshTypeT	fifoSvcThreshold,
	XllpMslFifoServiceTypeT		fifoServiceType
)
{
	XLLP_UINT32_T				channelCfg;
	XLLP_UINT32_T				bitsToClear;
	XLLP_UINT32_T				bitsToSet;

	//
	// Set the specified receive configuration in BBCFG for the specified channel
	//

	channelCfg = pMslRegBase->ConfigReg.BBCFG[channel];

	bitsToClear= (0x1U << XLLP_MSL_BBCFG_TxEnable)			|
		         (0x1U << XLLP_MSL_BBCFG_TxMFCEnable)		|
				 (0x1U << XLLP_MSL_BBCFG_TxDFCEnable)		|
				 (0x3U << XLLP_MSL_BBCFG_TxThreshLevel)		|
				 (0x7U << XLLP_MSL_BBCFG_TxService);

	bitsToSet  = (txChannelEnable << XLLP_MSL_BBCFG_TxEnable)		|
		         (txMfcEnable     << XLLP_MSL_BBCFG_TxMFCEnable)	|
				 (txDfcEnable     << XLLP_MSL_BBCFG_TxDFCEnable)	|
				 (fifoSvcThreshold<< XLLP_MSL_BBCFG_TxThreshLevel)	|
				 (fifoServiceType << XLLP_MSL_BBCFG_TxService);

	XLLP_CLEAR_BITS(channelCfg, bitsToClear);
	XLLP_SET_BITS  (channelCfg, bitsToSet);
	
	pMslRegBase->ConfigReg.BBCFG[channel] = channelCfg;

	return;	
}

void XllpMslSetTxFifoService
(
	P_XllpMslRegT				pMslRegBase,
	XLLP_INT32_T				channel,
    XLLP_UINT32_T               fifoService
)
{
	XLLP_UINT32_T				channelCfg;
	XLLP_UINT32_T				bitsToClear=0;
    XLLP_UINT32_T				bitsToSet=0;

    channelCfg = pMslRegBase->ConfigReg.BBCFG[channel];

    if(fifoService)
	    bitsToSet=   (fifoService << XLLP_MSL_BBCFG_TxService);
    else
        bitsToClear= (0x7U << XLLP_MSL_BBCFG_TxService);

	XLLP_CLEAR_BITS(channelCfg, bitsToClear);
    XLLP_SET_BITS  (channelCfg, bitsToSet);
	pMslRegBase->ConfigReg.BBCFG[channel] = channelCfg;
}

void XllpMslSetRxFifoService
(
	P_XllpMslRegT				pMslRegBase,
	XLLP_INT32_T				channel,
    XLLP_UINT32_T               fifoService
)
{
	XLLP_UINT32_T				channelCfg;
    XLLP_UINT32_T				bitsToClear=0;
    XLLP_UINT32_T				bitsToSet=0;

    channelCfg = pMslRegBase->ConfigReg.BBCFG[channel];

    if(fifoService)
	    bitsToSet=   (fifoService << XLLP_MSL_BBCFG_RxService);
    else
	    bitsToClear= (0x7U << XLLP_MSL_BBCFG_RxService);

	XLLP_CLEAR_BITS(channelCfg, bitsToClear);
    XLLP_SET_BITS  (channelCfg, bitsToSet);
	pMslRegBase->ConfigReg.BBCFG[channel] = channelCfg;
}

void XllpMslGetChannelStatus  
( 
	P_XllpMslRegT				pMslRegBase,
	XLLP_INT32_T				channel,
	XLLP_UINT32_T				*status
)
{
	*status = pMslRegBase->StatusReg.BBSTAT[channel];
	return;
}

void XllpMslGetInterruptStatus
(
	P_XllpMslRegT				pMslRegBase,
	XLLP_UINT32_T				*interruptStatus
)
{
	*interruptStatus = pMslRegBase->ControlReg.BBIID;
	return;
}

void XllpMslClearInterrupts	  
(
	P_XllpMslRegT				pMslRegBase,
	XLLP_UINT32_T				interruptMask
)
{
	pMslRegBase->ControlReg.BBIID = interruptMask;
	return;
}

void XllpMslSendWake		   
(
	P_XllpMslRegT				pMslRegBase 
)
{
	//
	// Write anything to WAKE register 
	//
	pMslRegBase->ControlReg.BBWAKE = XLLP_SET;
	return;
}

void XllpMslSendEOM			   
(
	P_XllpMslRegT				pMslRegBase,
	XLLP_UINT32_T				channel
)
{
	//
	// Write anything to EOM register for this particular channel
	//
	pMslRegBase->EomReg.BBEOM[channel] = XLLP_SET;
	return;
}

XLLP_LEVEL_T XllpMslGetVgpioLevel	   
(
	P_XllpMslRegT				pMslRegBase,
	XllpVgpioPinTypeT			pinType,
	XLLP_UINT32_T				pinNumber
)
{
	XLLP_LEVEL_T				pinLevel;

	if (pinType == OutputVgpioPin)
	{
		pinLevel = ((pMslRegBase->ControlReg.BBVGOL) & (1 << pinNumber)) ? XLLP_HI : XLLP_LO;
	}
	else
	{
		pinLevel = ((pMslRegBase->ControlReg.BBVGIL) & (1 << pinNumber)) ? XLLP_HI : XLLP_LO;
	}
	return (pinLevel);
}

void XllpMslSetVgpioLevel	   
(
	P_XllpMslRegT				pMslRegBase,
	XLLP_UINT32_T				pinNumber,
	XLLP_LEVEL_T				pinLevel
)
{
	if (pinNumber >= XLLP_MSL_MAX_VGPIO_PINS)
		return;

	if (pinLevel == XLLP_HI)
	  pMslRegBase->ControlReg.BBVGSR  = (1 << pinNumber);
	else
	  pMslRegBase->ControlReg.BBVGCR  = (1 << pinNumber);

	return;
}

						  
void XllpMslConfigureVgpioEdgeDetect
(
	P_XllpMslRegT			pMslRegBase,
	XLLP_UINT32_T			pinNumber,
	XllpMslVgpioEdgeTypeT	pinEdgeType
)
{
	//
	// First clear current settings
	//
	pMslRegBase->ControlReg.BBVGRE = pMslRegBase->ControlReg.BBVGRE & (~(1 << pinNumber));
	pMslRegBase->ControlReg.BBVGFE = pMslRegBase->ControlReg.BBVGFE & (~(1 << pinNumber));

	if (pinEdgeType == VgpioRisingEdge)
	{
	  pMslRegBase->ControlReg.BBVGRE = pMslRegBase->ControlReg.BBVGRE | (1 << pinNumber);
	}
	else if (pinEdgeType == VgpioFallingEdge)
	{
	  pMslRegBase->ControlReg.BBVGFE = pMslRegBase->ControlReg.BBVGFE | (1 << pinNumber);
	}
	else if (pinEdgeType == VgpioRisingAndFallingEdge)
	{
	  pMslRegBase->ControlReg.BBVGRE = pMslRegBase->ControlReg.BBVGRE | (1 << pinNumber);
	  pMslRegBase->ControlReg.BBVGFE = pMslRegBase->ControlReg.BBVGFE | (1 << pinNumber);
	}

	return;
}

XLLP_BOOL_T XllpMslGetVgpioEdgeStatus 
(
	P_XllpMslRegT				pMslRegBase,
	XLLP_UINT32_T				inputPinNumber
)
{
	XLLP_BOOL_T	status;

    if (pMslRegBase->ControlReg.BBVGED & (1 << inputPinNumber))
	{
		status = XLLP_TRUE;	
		pMslRegBase->ControlReg.BBVGED = (1 << inputPinNumber);	// clear status
	}
	else
		status = XLLP_FALSE;

	return (status);
}

void XllpMslConfigureVgpioValueInterrupt
(
	P_XllpMslRegT			pMslRegBase,
	XLLP_CONTROL_T			offOrOn
)
{
    pMslRegBase->ControlReg.BBVGVI = (offOrOn & 0x1);
	return;
}