xllp_pm_sleepreglists.c

Xcale270Bsp包,wince平台

/******************************************************************************
**
** INTEL CONFIDENTIAL
** Copyright 2000-2003 Intel Corporation All Rights Reserved.
**
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** related to the source code (Material) are owned by Intel Corporation
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**
**  FILENAME:   xllp_Pm_SleepReglists.c
**
**  PURPOSE:    contains register lists needed for the XllpPmEnterSleep() complex.
**
******************************************************************************/

#include "xllp_defs.h"
#include "xllp_Pm_OsSpecific.h"    // Defines interesting virtual base addresses of interesting register sets on a per-OS basis
#include "xllp_Pm_ProcRegInfo.h"        // Defines register masks and offsets from base address for specific processor
#include "xllp_Pm.h"
#include "xllp_bcr.h"
#include "xllp_intc.h"
#include "xllp_gpio.h"
#include "xllp_Pm_SleepContext.h"

//#define getoffset(x,y) ((XLLP_UINT32_T)&(((x*)0)->y))

XLLP_PM_ADDR_WITH_MASK_T XllpPmSleepStdRegList [XLLP_PM_SLEEP_STD_REGLIST_CNT] =
{
    
//    {(P_XLLP_UINT32_T) (XLLP_U_V_IM_REGS_BASE + XLLP_OFFS_IMPMCR),        XLLP_VLD_MSK_IMPMCR} ,

    // PGSRx regs will be restored, but must be modified before being saved
    {(P_XLLP_VUINT32_T) (XLLP_U_V_PWRMGR_BASE + (XLLP_UINT32_T)&(((XLLP_PWRMGR_T*)0)->PGSR0)), XLLP_PM_PGSR0_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_PWRMGR_BASE + (XLLP_UINT32_T)&(((XLLP_PWRMGR_T*)0)->PGSR1)), XLLP_PM_PGSR1_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_PWRMGR_BASE + (XLLP_UINT32_T)&(((XLLP_PWRMGR_T*)0)->PGSR2)), XLLP_PM_PGSR2_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_PWRMGR_BASE + (XLLP_UINT32_T)&(((XLLP_PWRMGR_T*)0)->PGSR3)), XLLP_PM_PGSR3_VLD_MSK} ,

    // Note: These registers are not affected by sleep or deep sleep: PSTR, PSNR
    // Note: All DVM-related registers are left to the control of the

    //(note GPLRs values can't be copied directly back, 
    // so saving that register via the list doesn't work)

    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GPDR0)), XLLP_GPIO_GPDR0_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GPDR1)), XLLP_GPIO_GPDR1_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GPDR2)), XLLP_GPIO_GPDR2_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GPDR3)), XLLP_GPIO_GPDR3_VLD_MSK} ,

    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GAFR0_L)), XLLP_GPIO_GAFR0_L_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GAFR0_U)), XLLP_GPIO_GAFR0_U_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GAFR1_L)), XLLP_GPIO_GAFR1_L_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GAFR1_U)), XLLP_GPIO_GAFR1_U_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GAFR2_L)), XLLP_GPIO_GAFR2_L_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GAFR2_U)), XLLP_GPIO_GAFR2_U_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GAFR3_L)), XLLP_GPIO_GAFR3_L_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GAFR3_U)), XLLP_GPIO_GAFR3_U_VLD_MSK} ,

    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GRER0)), XLLP_GPIO_GRER0_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GRER1)), XLLP_GPIO_GRER1_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GRER2)), XLLP_GPIO_GRER2_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GRER3)), XLLP_GPIO_GRER3_VLD_MSK} ,

    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GFER0)), XLLP_GPIO_GFER0_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GFER1)), XLLP_GPIO_GFER1_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GFER2)), XLLP_GPIO_GFER2_VLD_MSK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_GPIO_BASE + (XLLP_UINT32_T)&(((XLLP_GPIO_T*)0)->GFER3)), XLLP_GPIO_GFER3_VLD_MSK} ,

#ifndef XLLP_PM_SLEEP_SKIP_BLR_SAVES
  #ifdef BSP_MAINSTONE_II
    // Note: this section is a good candidate for moving
    //  to a special platform-specific file and list.
    {(P_XLLP_VUINT32_T) (XLLP_U_V_FPGA_BASE + (XLLP_UINT32_T)&(((XLLP_BCR_T*)0)->HLDR1)), XLLP_BCR_HEXLED1_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_FPGA_BASE + (XLLP_UINT32_T)&(((XLLP_BCR_T*)0)->HLDR2)), XLLP_BCR_HEXLED2_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_FPGA_BASE + (XLLP_UINT32_T)&(((XLLP_BCR_T*)0)->LCR)), XLLP_BCR_LEDCTRL_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_FPGA_BASE + (XLLP_UINT32_T)&(((XLLP_BCR_T*)0)->MISCWR1)), XLLP_BCR_MISCWR1_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_FPGA_BASE + (XLLP_UINT32_T)&(((XLLP_BCR_T*)0)->MISCWR2)), XLLP_BCR_MISCWR2_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_FPGA_BASE + (XLLP_UINT32_T)&(((XLLP_BCR_T*)0)->MISCWR3)), XLLP_BCR_MISCWR3_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_FPGA_BASE + (XLLP_UINT32_T)&(((XLLP_BCR_T*)0)->PIMER1)), XLLP_BCR_INTMASK_ENABLE_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_FPGA_BASE + (XLLP_UINT32_T)&(((XLLP_BCR_T*)0)->PCMCIAS0SCR)), XLLP_BCR_PCMCIA_SCR_S0_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_FPGA_BASE + (XLLP_UINT32_T)&(((XLLP_BCR_T*)0)->PCMCIAS1SCR)), XLLP_BCR_PCMCIA_SCR_S1_MASK} ,
    // Don't touch FPGA scratch registers - supposed to last through sleep.

  #endif // def BSP_MAINSTONE_II
#endif // ndef XLLP_PM_SLEEP_SKIP_BLR_SAVES

    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->iclr)), XLLP_INTC_ICLR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->iclr2)), XLLP_INTC_ICLR2_MASK} ,

    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->iccr)), XLLP_INTC_ICCR_MASK} ,

    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[0])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[1])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[2])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[3])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[4])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[5])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[6])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[7])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[8])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[9])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[10])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[11])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[12])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[13])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[14])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[15])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[16])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[17])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[18])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[19])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[20])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[21])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[22])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[23])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[24])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[25])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[26])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[27])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[28])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[29])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[30])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr[31])), XLLP_INTC_IPR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr2[0])), XLLP_INTC_IPR2_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->ipr2[1])), XLLP_INTC_IPR2_MASK} ,

    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->icmr)), XLLP_INTC_ICMR_MASK} ,
    {(P_XLLP_VUINT32_T) (XLLP_U_V_INTC_BASE + (XLLP_UINT32_T)&(((XLLP_INTC_T*)0)->icmr2)), XLLP_INTC_ICMR2_MASK} ,


}; // XllpPmSleepStdRegList

#if    XLLP_PM_SLEEP_DEEP_REGLIST_CNT

XLLP_PM_ADDR_WITH_MASK_T XllpPmSleepDeepRegList [/*XLLP_PM_SLEEP_DEEP_REGLIST_CNT*/] =
{
    
};

#endif //   XLLP_PM_SLEEP_DEEP_REGLIST_CNT