📄 xlli_bulverde_defs.inc
字号:
;*********************************************************************************
;
; COPYRIGHT (c) 2002 Intel Corporation
;
; The information in this file is furnished for informational use only,
; is subject to change without notice, and should not be construed as
; a commitment by Intel Corporation. Intel Corporation assumes no
; responsibility or liability for any errors or inaccuracies that may appear
; in this document or any software that may be provided in association with
; this document.
;
;*********************************************************************************
;
; FILENAME: xlli_Bulverde_defs.inc (Core processor address definitions)
;
; LAST MODIFIED: 14-Oct-2003
;
;******************************************************************************
;
;
; Include file for Bulverde Processor based
; Cross Platform Low Level Initialization (XLLI)
;
;
; GENERAL PURPOSE I/O (GPIO) base address and register offsets from the base address
;
xlli_GPIOREGS_PHYSICAL_BASE EQU 0x40E00000
; GPIO register offsets from the base address
xlli_GPLR0_offset EQU (0x000) ; GPIO Level registers
xlli_GPLR1_offset EQU (0x004)
xlli_GPLR2_offset EQU (0x008)
xlli_GPLR3_offset EQU (0x100)
xlli_GPDR0_offset EQU (0x00C) ; GPIO Direction registers
xlli_GPDR1_offset EQU (0x010)
xlli_GPDR2_offset EQU (0x014)
xlli_GPDR3_offset EQU (0x10C)
xlli_GPSR0_offset EQU (0x018) ; GPIO Set registers
xlli_GPSR1_offset EQU (0x01C)
xlli_GPSR2_offset EQU (0x020)
xlli_GPSR3_offset EQU (0x118)
xlli_GPCR0_offset EQU (0x024) ; GPIO Clear registers
xlli_GPCR1_offset EQU (0x028)
xlli_GPCR2_offset EQU (0x02C)
xlli_GPCR3_offset EQU (0x124)
xlli_GAFR0_L_offset EQU (0x054) ; GPIO Alternate function registers (Bits 15:0)
xlli_GAFR0_U_offset EQU (0x058) ; Bits 31:16
xlli_GAFR1_L_offset EQU (0x05c) ; Bits 47:32
xlli_GAFR1_U_offset EQU (0x060) ; Bits 63:48
xlli_GAFR2_L_offset EQU (0x064) ; Bits 79:64
xlli_GAFR2_U_offset EQU (0x068) ; Bits 95:80
xlli_GAFR3_L_offset EQU (0x06C) ; Bits 111:96
xlli_GAFR3_U_offset EQU (0x070) ; Bits 127:112
;
; POWER MANAGER base address and register offsets from the base address
;
xlli_PMRCREGS_PHYSICAL_BASE EQU 0x40F00000
xlli_PMCR_offset EQU (0x00) ; Power Manager Control Register
xlli_PSSR_offset EQU (0x04) ; Power Manager Sleep Status Register
xlli_PSPR_offset EQU (0x08) ; Power Manager Scratch Pad Register
xlli_PWER_offset EQU (0x0C) ; Power Manager Wake-up Enable Register
xlli_PRER_offset EQU (0x10) ; Power Manager GPIO Rising-edge Detect Enable Register
xlli_PFER_offset EQU (0x14) ; Power Manager GPIO Falling-edge Detect Enable Register
xlli_PEDR_offset EQU (0x18) ; Power Manager GPIO Edge Detect Status Register
xlli_PCFR_offset EQU (0x1C) ; Power Manager General Configuration Register
xlli_PGSR0_offset EQU (0x20) ; Power Manager GPIO Sleep State Register for GP [31-0]
xlli_PGSR1_offset EQU (0x24) ; Power Manager GPIO Sleep State Register for GP [63-32]
xlli_PGSR2_offset EQU (0x28) ; Power Manager GPIO Sleep State Register for GP [95-64]
xlli_PGSR3_offset EQU (0x2C) ; Power Manager GPIO Sleep State Register for GP [120-96]
xlli_RCSR_offset EQU (0x30) ; Reset Controller Status Register
xlli_PSLR_offset EQU (0x34) ; Power Manager Sleep Mode Config Register
xlli_PSTR_offset EQU (0x38) ; Power Manager Standby Mode Config Register
xlli_PSNR_offset EQU (0x3C) ; Power Manager Sense Moce Config Register
xlli_PVCR_offset EQU (0x40) ; Power Manager Voltage Change Control Register
xlli_PKWR_offset EQU (0x50) ; Power Manager Keyboard Wake-up Enable Register
xlli_PKSR_offset EQU (0x54) ; Power Manager Keyboard Edge-Detect Status Register
xlli_PI2DBR_offset EQU (0x188) ; Power I2C Data Buffer Register
xlli_PI2CR_offset EQU (0x190) ; Power I2C Control Register
xlli_PI2SR_offset EQU (0x198) ; Power I2C Status Register
xlli_PI2SAR_offset EQU (0x1A0) ; Power I2C Slave Address Register
;
; POWER MANAGER register bit masks
;
xlli_PSSR_SSS EQU (0x01) ; Software Sleep Status
xlli_PSSR_BFS EQU (0x02) ; Battery Fault Status
xlli_PSSR_VFS EQU (0x04) ; VCC Fault Status
xlli_PSSR_PH EQU (0x10) ; Peripheral Control Hold
xlli_PSSR_RDH EQU (0x20) ; Read Disable Hold
xlli_PCFR_OPDE EQU (0x01) ; Processor (13MHz) osc power-down enable
xlli_PCFR_FP EQU (0x02) ; Float PCMCIA during sleep modes
xlli_PCFR_FS EQU (0x04) ; Float Static Chip Selects
xlli_PCFR_SYSEN_EN EQU (0x20) ; SYS_EN pin
xlli_PCFR_DC_EN EQU (0x80) ; Deep-Sleep Mode
xlli_PWER_WE0 EQU (0x01) ; Wake-up Enable GPIO pin 0
xlli_PWER_WE1 EQU (0x02) ; Wake-up Enable GPIO pin 1
xlli_PWER_WERTC EQU (0x80000000); RTC Standby, Wake-up Enable-
;
; MEMORY CONTROLLER base address and register offsets from the base address
;
xlli_MEMORY_CONFIG_BASE EQU 0x48000000
xlli_MDCNFG_offset EQU (0x00)
xlli_MDREFR_offset EQU (0x04)
xlli_MSC0_offset EQU (0x08)
xlli_MSC1_offset EQU (0x0C)
xlli_MSC2_offset EQU (0x10)
xlli_MECR_offset EQU (0x14)
xlli_SXLCR_offset EQU (0x18)
xlli_SXCNFG_offset EQU (0x1C)
xlli_FLYCNFG_offset EQU (0x20)
xlli_SXMRS_offset EQU (0x24)
xlli_MCMEM0_offset EQU (0x28)
xlli_MCMEM1_offset EQU (0x2C)
xlli_MCATT0_offset EQU (0x30)
xlli_MCATT1_offset EQU (0x34)
xlli_MCIO0_offset EQU (0x38)
xlli_MCIO1_offset EQU (0x3C)
xlli_MDMRS_offset EQU (0x40)
xlli_BOOT_DEF_offset EQU (0x44)
xlli_ARB_CNTL_offset EQU (0x48)
xlli_BSCNTR0_offset EQU (0x4C)
xlli_BSCNTRN_offset EQU (0x50)
xlli_LCDBSCNTR_offset EQU (0x54)
xlli_MDMRSLP_offset EQU (0x58)
xlli_BSCNTR3_offset EQU (0x60)
; Memory Controller bit defs
xlli_MDREFR_K0DB4 EQU (0x20000000) ; Sync Static Clock 0 divide by 4 control/status
xlli_MDREFR_K2FREE EQU (0x02000000) ; Set to force SDCLK[2] to be free running
xlli_MDREFR_K1FREE EQU (0x01000000) ; Set to force SDCLK[1] to be free running
xlli_MDREFR_K0FREE EQU (0x00800000) ; Set to force SDCLK[0] to be free running
xlli_MDREFR_SLFRSH EQU (0x00400000) ; Self Refresh Control Status bit
xlli_MDREFR_APD EQU (0x00100000) ; Auto Power Down bit
xlli_MDREFR_K2DB2 EQU (0x00080000) ; SDRAM clock pin 2 divide by 2 control/status
xlli_MDREFR_K1DB2 EQU (0x00020000) ; SDRAM clock pin 1 divide by 2 control/status
xlli_MDREFR_K1RUN EQU (0x00010000) ; SDRAM clock pin 1 run/control status
xlli_MDREFR_E1PIN EQU (0x00008000) ; SDRAM clock Enable pin 1 level control/status
xlli_MDREFR_K0DB2 EQU (0x00004000) ; Sync Static Memory Clock divide by 2 control/status
xlli_MDREFR_K0RUN EQU (0x00002000) ; Sync Static Memory Clock Pin 0
xlli_MDREFR_E0PIN EQU (0x00000100) ; SDRAM clock enable pin 0 (Cotulla ONLY!!)
xlli_MDCNFG_DE0 EQU (0x00000001) ; SDRAM enable bit for partition 0
xlli_MDCNFG_DE1 EQU (0x00000002) ; SDRAM enable bit for partition 1
xlli_MDCNFG_DE2 EQU (0x00010000) ; SDRAM enable bit for partition 2
xlli_MDCNFG_DE3 EQU (0x00020000) ; SDRAM enable bit for partition 3
xlli_MDCNFG_DWID0 EQU (0x00000004) ; SDRAM bus width (clear = 32 bits, set = 16 bits)
;
; INTERNAL MEMORY CONTROLLER base address and register offsets from the base address
;
xlli_IMEMORY_CONFIG_BASE EQU (0x58000000)
xlli_IMPMCR_offset EQU (0x00) ; Internal Memory Power Manager Control Register
xlli_IMPMSR_offset EQU (0x08) ; Internal Memory Power Management Status Register
;
; INTERRUPT CONTROLLER base address and register offsets from the base address
;
xlli_INTERREGS_PHYSICAL_BASE EQU (0x40D00000)
xlli_ICIP_offset EQU (0x00) ; Interrupt Controller IRQ Pending Register
xlli_ICMR_offset EQU (0x04) ; Interrupt Controller Mask Register
xlli_ICLR_offset EQU (0x08) ; Interrupt Controller Level Register
xlli_ICFP_offset EQU (0x0C) ; Interrupt Controller FIQ pending Register
xlli_ICPR_offset EQU (0x10) ; Interrupt Controller Pending Register
xlli_ICCR_offset EQU (0x14) ; Interrupt Controller Control Register
xlli_ICHP_offset EQU (0x18) ; Interrupt Controller Highest Priority Reg
xlli_ICMR2_offset EQU (0xA0) ; Interrupt Controller Mask Register 2
xlli_ICLR2_offset EQU (0xA4) ; Interrupt Controller Level Register 2
xlli_ICCR2_offset EQU (0xAC) ; Interrupt Controller Control Register 2
;
; CLOCK REGISTERS base address and register offsets from the base address
;
xlli_CLKREGS_PHYSICAL_BASE EQU (0x41300000)
xlli_CCCR_offset EQU (0x00) ; Core Clock Configuration Register
xlli_CKEN_offset EQU (0x04) ; Clock-Enable Register
xlli_OSCC_offset EQU (0x08) ; Oscillator Configuration Register
xlli_CCSR_offset EQU (0x0C) ; Core Clock Status Register
xlli_CCCR_A_Bit_Mask EQU (0x1 << 25) ; "A" bit is bit 25 in CCCR
;
; OS TIMER REGISTERS base address and register offsets from the base address
;
xlli_OSTREGS_PHYSICAL_BASE EQU (0x40A00000)
xlli_OSMR0_offset EQU (0x00) ; OS Timer Match Register 0
xlli_OSMR1_offset EQU (0x04) ; OS Timer Match Register 1
xlli_OSMR2_offset EQU (0x08) ; OS Timer Match Register 2
xlli_OSMR3_offset EQU (0x0C) ; OS Timer Match Register 3
xlli_OSCR0_offset EQU (0x10) ; OS Timer Count Register 0
xlli_OSSR_offset EQU (0x14) ; OS Timer Status Register
xlli_OWER_offset EQU (0x18) ; OS Timer Watchdog Enable Register
xlli_OIER_offset EQU (0x1C) ; OS Timer Interrupt Enable Register
xlli_OSCR4_offset EQU (0x40) ; OS Timer Count Register 4
xlli_OSCR5_offset EQU (0x44) ; OS Timer Count Register 5
xlli_OSCR6_offset EQU (0x48) ; OS Timer Count Register 6
xlli_OSCR7_offset EQU (0x4C) ; OS Timer Count Register 7
xlli_OSCR8_offset EQU (0x50) ; OS Timer Count Register 8
xlli_OSCR9_offset EQU (0x54) ; OS Timer Count Register 9
xlli_OSCR10_offset EQU (0x58) ; OS Timer Count Register 10
xlli_OSCR11_offset EQU (0x5C) ; OS Timer Count Register 11
xlli_OSMR4_offset EQU (0x80) ; OS Timer Match Register 4
xlli_OSMR5_offset EQU (0x84) ; OS Timer Match Register 5
xlli_OSMR6_offset EQU (0x88) ; OS Timer Match Register 6
xlli_OSMR7_offset EQU (0x8C) ; OS Timer Match Register 7
xlli_OSMR8_offset EQU (0x90) ; OS Timer Match Register 8
xlli_OSMR9_offset EQU (0x94) ; OS Timer Match Register 9
xlli_OSMR10_offset EQU (0x98) ; OS Timer Match Register 10
xlli_OSMR11_offset EQU (0x9C) ; OS Timer Match Register 11
xlli_OMCR4_offset EQU (0xC0) ; OS Timer Match Control Register 4
xlli_OMCR5_offset EQU (0xC4) ; OS Timer Match Control Register 5
xlli_OMCR6_offset EQU (0xC8) ; OS Timer Match Control Register 6
xlli_OMCR7_offset EQU (0xCC) ; OS Timer Match Control Register 7
xlli_OMCR8_offset EQU (0xD0) ; OS Timer Match Control Register 8
xlli_OMCR9_offset EQU (0xD4) ; OS Timer Match Control Register 9
xlli_OMCR10_offset EQU (0xD8) ; OS Timer Match Control Register 10
xlli_OMCR11_offset EQU (0xDC) ; OS Timer Match Control Register 11
xlli_OSSR_ALL EQU (0xFFF) ; Match register status "sticky bits"
xlli_OIER_E1 EQU (0x002) ; Interrupt enable bit for match register #1
;
; REAL TIME CLOCK (RTC) REGISTERS base address and register offsets from the base address
;
xlli_RTCREGS_PHYSICAL_BASE EQU (0x04090000)
xlli_RCNR_offset EQU (0x00) ; RTC Counter Register
xlli_RTAR_offset EQU (0x04) ; RTC Alarm Register
xlli_RTSR_offset EQU (0x08) ; RTC Status Register
xlli_RTTR_offset EQU (0x0C) ; RTC Timer Trim Register
xlli_RDCR_offset EQU (0x10) ; RTC Day Counter Register
xlli_RYCR_offset EQU (0x14) ; RTC Year Counter Register
xlli_RDAR1_offset EQU (0x18) ; RTC Day Alarm Register 1
xlli_RYAR1_offset EQU (0x1C) ; RTC Year Alarm Register 2
xlli_RDAR2_offset EQU (0x20) ; RTC Day Alarm Register 2
xlli_RYAR2_offset EQU (0x24) ; RTC Year Alarm Register 2
xlli_SWCR_offset EQU (0x28) ; Stopwatch Counter Register
xlli_SWAR1_offset EQU (0x2C) ; Stopwatch Alarm Register 1
xlli_SWAR2_offset EQU (0x30) ; Stopwatch Alarm Register 2
xlli_PICR_offset EQU (0x34) ; Periodic Interrupt Counter Register
xlli_PIAR_offset EQU (0x38) ; Periodic Interrupt Alarm Register
; Interrupt Controller bit defs
xlli_OSCC_OOK EQU (0x01) ; Oscillator OK bit
xlli_OSCC_OON EQU (0x02) ; Timekeeping (32.768KHz) Osc bit
xlli_OSCC_TOUT_EN EQU (0x04) ; Timekeeping Output enable
xlli_OSCC_PIO_EN EQU (0x08) ; Processor Oscillator Output Enable
;
; Coprocessor 15 data bits
;
xlli_control_icache EQU (0x1000) ; bit 12 - i-cache bit
xlli_control_btb EQU (0x0800) ; bit 11 - btb bit
xlli_control_r EQU (0x0200) ; Bit 9
xlli_control_s EQU (0x0100) ; Bit 8
xlli_control_dcache EQU (0x0004) ; Bit 2 - d-cache bit
xlli_control_mmu EQU (0x0001) ; Bit 0 - MMU bit
;
; CP 15 related settings
;
xlli_PID EQU (0x00)
xlli_DACR EQU (0x01)
xlli_CONTROL_DCACHE EQU (0x04)
xlli_CONTROL_MINIDATA_01 EQU (0x10)
xlli_CONTROL_BTB EQU (0x800) ; Brach Target Buffer bit
;
; register bit masks - RCSR
;
xlli_RCSR_HWR EQU (0x01)
xlli_RCSR_WDR EQU (0x02)
xlli_RCSR_SMR EQU (0x04)
xlli_RCSR_GPR EQU (0x08)
xlli_RCSR_ALL EQU (0xF)
;
; CPSR Processor constants
xlli_CPSR_Mode_MASK EQU (0x0000001F)
xlli_CPSR_Mode_USR EQU (0x10)
xlli_CPSR_Mode_FIQ EQU (0x11)
xlli_CPSR_Mode_IRQ EQU (0x12)
xlli_CPSR_Mode_SVC EQU (0x13)
xlli_CPSR_Mode_ABT EQU (0x17)
xlli_CPSR_Mode_UND EQU (0x1B)
xlli_CPSR_Mode_SYS EQU (0x1F)
xlli_CPSR_I_Bit EQU (0x80)
xlli_CPSR_F_Bit EQU (0x40)
xlli_PWRMODE_SLEEP EQU (0x00000003) ; Value for cp14: Reg7 to induce sleep.
END
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -