📄 xlli_mainstone_defs.inc
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;*********************************************************************************
;
; COPYRIGHT (c) 2002, 2003 Intel Corporation
;
; The information in this file is furnished for informational use only,
; is subject to change without notice, and should not be construed as
; a commitment by Intel Corporation. Intel Corporation assumes no
; responsibility or liability for any errors or inaccuracies that may appear
; in this document or any software that may be provided in association with
; this document.
;
;*********************************************************************************
;
; FILENAME: xlli_Mainstone_defs.inc (Platform specific addresses and
; defalut values for Mainstone II platform bring up)
; NOTE: - This file is for the non-MCP version of the processor.
;
; LAST MODIFIED: 14-Oct-2003
;
;******************************************************************************
;
;
; Include file for Mainstone II specific Cross Platform Low Level Initialization (XLLI)
;
;
; PLATFORM REGISTERS base address and register offsets from the base address
;
xlli_PLATFORM_REGISTERS EQU 0x08000000
xlli_PLATFORM_HEXLED_DATA_offset EQU (0x10) ; Hex LED Data Register
xlli_PLATFORM_LED_CONTROL_offset EQU (0x40) ; LED Control Register
xlli_PLATFORM_SWITCH_offset EQU (0x60) ; General Purpose Switch Register
xlli_PLATFORM_MISC_WRITE1_offset EQU (0x80) ; Misc Write Register 1
xlli_PLATFORM_MISC_WRITE2_offset EQU (0x84) ; Misc Write Register 2
xlli_PLATFORM_MISC_READ1_offset EQU (0x90) ; Misc Read Register 1
xlli_PLATFORM_INTERR_ME_offset EQU (0xC0) ; Platform Interrupt Mask/Enable Register 1
xlli_PLATFORM_INTERR_SC_offset EQU (0xD0) ; Platform Interrupt Set/Clear Register 1
xlli_PLATFORM_PCMCIA0_SC_offset EQU (0xE0) ; PCMCIA Socket 0 Status/Control Register
xlli_PLATFORM_PCMCIA1_SC_offset EQU (0xE4) ; PCMCIA Socket 1 Status/Control Register
;
; Platform specific bits
;
xlli_SYS_RESET EQU (0x01) ; System reset bit
;
; platform GPIO pin settings (Bulverde/Mainstone)
;
;xlli_GPSR0_value EQU (0x00408800) ; Set registers
;xlli_GPSR1_value EQU (0x00000002) ;
;xlli_GPSR2_value EQU (0x0001FC00)
;xlli_GPSR3_value EQU (0x00000000)
;xlli_GPCR0_value EQU (0x0) ; Clear registers
;xlli_GPCR1_value EQU (0x0)
;xlli_GPCR2_value EQU (0x0)
;xlli_GPCR3_value EQU (0x0)
;xlli_GPDR0_value EQU (0x00088004) ; Direction Registers
;xlli_GPDR1_value EQU (0xFC000382)
;xlli_GPDR2_value EQU (0x00C17FFF)
;xlli_GPDR3_value EQU (0x00000000)
;xlli_GAFR0_L_value EQU (0x90000000) ; Alternate function registers
;xlli_GAFR0_U_value EQU (0x00000000)
;xlli_GAFR1_L_value EQU (0x000A9558)
;xlli_GAFR1_U_value EQU (0xAAA00000)
;xlli_GAFR2_L_value EQU (0x2AAAAAAA)
;xlli_GAFR2_U_value EQU (0x0000A002)
;xlli_GAFR3_L_value EQU (0x00000000)
;xlli_GAFR3_U_value EQU (0x00001400)
;YL-PXA27x use below, hzh
;0->Input,1->LAN91C111 IRQ,3->LCDPWREN,4->CAMERA PWRDN,
;9->IDE IRQ,10->NAND nCE,11->Buzzer,12->CIF_D7,13->ext.,14->CS8900 IRQ,15->nCS1
;16->LCD BK,17->CIF_D6,18->nWAIT,19->ST16C550 IRQ,20->DREQ,21->DVAL,22->USBD PULL-UP,23->CIF_MCLK
;24->CIF_FV,25->CIF_LV,26->CIF_PCLK,27->CIF_D0,28->AC97_BCLK,29->AC97_SDI,30->AC97_SDO,31->AC97_SYNC
;32->MMC_CLK,33->nCS5,34->FFRXD,35->FFCTS,36->FFDCD,37->FFDSR,38->FFRI,39->FFTXD
;40->FFDTR,41->FFRTS,42->BTRXD,43->BTTXD,44->BTCTS,45->BTRTS,46->IRRXD,47->IRTXD
;48->nPOE,49->nPWE,50->nPIOR,51->nPIOW,52->VS2,53->BVD2,54->nPCE2,55->nPREG
;56->nPWAIT,57->nIOIS16,58~63->LDD[0~5]
;64~77->LCD,78->nCS2,79->nCS3
;80->nCS4,81->PCMCIA RDY/nIRQ,82->VS1,83->nCD,84->BVD1,85->nPCE1,86->LDD[16],87->LDD[17]
;88->NAND R/nB,89->LED1,90->CIF_D4,91->CIF_D5,92->MMC_DAT0,93~95->KP_DKIN[0~2]
;96->LED4,97->KP_MKIN[3],98->MMC_nCD,99->MMC_WP,100~102->KP_MKIN[0~2],103->KP_MKOUT[0]
;104->KP_MKOUT[1],105->KP_MKOUT[2],106->ext.,107->LED2,108->LED3,109~111->MMC_DAT[1~3]
;112->MMC_CMD,113->AC97_nRST,114->CIF_D1,115->CIF_D3,116->CIF_D2,117->SCL,118->SDA,
;119,120 supported in PXA271,272,273 only!
xlli_GPSR0_value EQU (0x00008408) ; Set registers
xlli_GPSR1_value EQU (0x004FAB82)
xlli_GPSR2_value EQU (0x0021C000)
xlli_GPSR3_value EQU (0x00000000)
xlli_GPCR0_value EQU (0x00010810) ; Clear registers
xlli_GPCR1_value EQU (0x00000000) ; FFUART related
xlli_GPCR2_value EQU (0x00000000)
xlli_GPCR3_value EQU (0x00000000)
xlli_GPDR0_value EQU (0xC0A18DFC) ; Direction Registers
xlli_GPDR1_value EQU (0xFCDFAB83)
xlli_GPDR2_value EQU (0x02E1FFFF)
xlli_GPDR3_value EQU (0x00021B81)
xlli_GAFR0_L_value EQU (0x82000000) ; Alternate function registers
xlli_GAFR0_U_value EQU (0xA5E54018)
xlli_GAFR1_L_value EQU (0x999A955A)
xlli_GAFR1_U_value EQU (0xAAA5A0AA)
xlli_GAFR2_L_value EQU (0xAAAAAAAA)
xlli_GAFR2_U_value EQU (0x55F0A402)
xlli_GAFR3_L_value EQU (0x540A950C)
xlli_GAFR3_U_value EQU (0x00001599)
;
; MEMORY CONTROLLER SETTINGS FOR MAINSTONE
;
xlli_MDREFR_value EQU (0x0000001E)
xlli_MSC0_DC_value EQU (0x39F2A7A2) ; Bulverde Card Flash value
;xlli_MSC0_MS_value EQU (0x23F223F2) ; Mainstone Board Flash value
xlli_MSC0_MS_value EQU (0x23F2B8F2) ; Mainstone Board Flash value,hzh
xlli_MSC1_value EQU (0x0000A691)
xlli_MSC2_value EQU (0x0000B884)
xlli_MECR_value EQU (0x00000001)
;xlli_MCMEM0_value EQU (0x0001C391)
;xlli_MCMEM1_value EQU (0x0001C391)
;xlli_MCATT0_value EQU (0x0001C391)
;xlli_MCATT1_value EQU (0x0001C391)
;xlli_MCIO0_value EQU (0x0001C391)
;xlli_MCIO1_value EQU (0x0001C391)
;===hzh
xlli_MCMEM0_value EQU (0x0000C497)
xlli_MCMEM1_value EQU (0x0000C497)
xlli_MCATT0_value EQU (0x0000C497)
xlli_MCATT1_value EQU (0x0000C497)
xlli_MCIO0_value EQU (0x0000C497)
xlli_MCIO1_value EQU (0x0000C497)
;===
xlli_FLYCNFG_value EQU (0x00010001)
xlli_MDMRSLP_value EQU (0x0000C008)
xlli_SXCNFG_value EQU (0x40044004) ; Default value at boot up
;
; Optimal values for MSCO for various MemClk frequencies are listed below
; These values are for K3 async flash
;
xlli_MSC0_13 EQU (0x12101210)
xlli_MSC0_19 EQU (0x12101210)
xlli_MSC0_26 EQU (0x12201220) ; 26 MHz setting
xlli_MSC0_32 EQU (0x12201220)
xlli_MSC0_39 EQU (0x13301330) ; 39 MHz setting
xlli_MSC0_45 EQU (0x13301330)
xlli_MSC0_52 EQU (0x13401340) ; 52 MHz setting
xlli_MSC0_58 EQU (0x13601360)
xlli_MSC0_65 EQU (0x13501350) ; 65 MHz setting
xlli_MSC0_68 EQU (0x13501350)
xlli_MSC0_71 EQU (0x14601460) ; 71.5 MHz setting
xlli_MSC0_74 EQU (0x14601460)
xlli_MSC0_78 EQU (0x14601460) ; 78 MHz setting
xlli_MSC0_81 EQU (0x14701470)
xlli_MSC0_84 EQU (0x14701470) ; 84.5 MHz setting
xlli_MSC0_87 EQU (0x14701470)
xlli_MSC0_91 EQU (0x14701470) ; 91 MHz setting
xlli_MSC0_94 EQU (0x14801480) ; 94.2 MHz setting
xlli_MSC0_97 EQU (0x14801480) ; 97.5 MHz setting
xlli_MSC0_100 EQU (0x15801580) ; 100.7 MHz setting
;xlli_MSC0_104 EQU (0x15801580) ; 104 MHz setting
xlli_MSC0_104 EQU (0x15802AD0) ; 104 MHz setting, hzh
xlli_MSC0_110 EQU (0x15901590)
xlli_MSC0_117 EQU (0x15A015A0) ; 117 MHz setting
xlli_MSC0_124 EQU (0x15A015A0)
xlli_MSC0_130 EQU (0x15B015B0) ; 130 MHz setting
xlli_MSC0_136 EQU (0x16B016B0)
xlli_MSC0_143 EQU (0x16C016C0)
xlli_MSC0_149 EQU (0x16C016C0)
xlli_MSC0_156 EQU (0x16C016C0)
xlli_MSC0_162 EQU (0x16C016C0)
xlli_MSC0_169 EQU (0x17D017D0) ; Given that the optimal value would be 13 (RDF), but according to B0 manual, it's different
xlli_MSC0_175 EQU (0x17C017C0)
xlli_MSC0_182 EQU (0x17C017C0)
xlli_MSC0_188 EQU (0x17D017D0)
xlli_MSC0_195 EQU (0x17E017E0)
xlli_MSC0_201 EQU (0x18E018E0)
;xlli_MSC0_208 EQU (0x18E018E0)
xlli_MSC0_208 EQU (0x18E02AF0) ;hzh
;
; Optimal values for DTC settings for various MemClk settings (MDCNFG)
;
xlli_DTC_13 EQU (0x00000000) ; 13 MHz setting
xlli_DTC_19 EQU (0x00000000) ; 19 MHz setting
xlli_DTC_26 EQU (0x00000000) ; 26 MHz setting
xlli_DTC_32 EQU (0x00000000) ; 32 MHz setting
xlli_DTC_39 EQU (0x00000000) ; 39 MHz setting
xlli_DTC_45 EQU (0x00000000) ; 45 MHz setting
xlli_DTC_52 EQU (0x00000000) ; 52 MHz setting
xlli_DTC_58 EQU (0x01000100) ; 58 MHz setting
xlli_DTC_65 EQU (0x01000100) ; 65 MHz setting
xlli_DTC_68 EQU (0x01000100) ; 68 MHz setting
xlli_DTC_71 EQU (0x01000100) ; 71 MHz setting
xlli_DTC_74 EQU (0x01000100) ; 74 MHz setting
xlli_DTC_78 EQU (0x01000100) ; 78 MHz setting
xlli_DTC_81 EQU (0x01000100) ; 81 MHz setting
xlli_DTC_84 EQU (0x01000100) ; 84 MHz setting
xlli_DTC_87 EQU (0x01000100) ; 87 MHz setting
xlli_DTC_91 EQU (0x01000100) ; 91 MHz setting
xlli_DTC_94 EQU (0x01000100) ; 94 MHz setting
xlli_DTC_97 EQU (0x01000100) ; 97 MHz setting
xlli_DTC_100 EQU (0x01000100) ; 100 MHz setting
xlli_DTC_104 EQU (0x01000100) ; 104 MHz setting
xlli_DTC_110 EQU (0x01000100) ; 110 MHz setting - SDCLK Halved
xlli_DTC_117 EQU (0x01000100) ; 117 MHz setting - SDCLK Halved
xlli_DTC_124 EQU (0x01000100) ; 124 MHz setting - SDCLK Halved
xlli_DTC_130 EQU (0x01000100) ; 130 MHz setting - SDCLK Halved
xlli_DTC_136 EQU (0x01000100) ; 136 MHz setting - SDCLK Halved
xlli_DTC_143 EQU (0x01000100) ; 143 MHz setting - SDCLK Halved
xlli_DTC_149 EQU (0x01000100) ; 149 MHz setting - SDCLK Halved
xlli_DTC_156 EQU (0x01000100) ; 156 MHz setting - SDCLK Halved
xlli_DTC_162 EQU (0x01000100) ; 162 MHz setting - SDCLK Halved
xlli_DTC_169 EQU (0x01000100) ; 169 MHz setting - SDCLK Halved
xlli_DTC_175 EQU (0x01000100) ; 175 MHz setting - SDCLK Halved
xlli_DTC_182 EQU (0x01000100) ; 182 MHz setting - SDCLK Halved
xlli_DTC_188 EQU (0x01000100) ; 188 MHz setting - SDCLK Halved
xlli_DTC_195 EQU (0x01000100) ; 195 MHz setting - SDCLK Halved
xlli_DTC_201 EQU (0x01000100) ; 201 MHz setting - SDCLK Halved
xlli_DTC_208 EQU (0x01000100) ; 208 MHz setting - SDCLK Halved
;
; Optimal values for DRI settings for various MemClk settings (MDREFR)
;
xlli_DRI_13 EQU (0x002) ; 13 MHz setting
xlli_DRI_19 EQU (0x003)
xlli_DRI_26 EQU (0x005) ; 26 MHz setting
xlli_DRI_32 EQU (0x006)
xlli_DRI_39 EQU (0x008) ; 39 MHz setting
xlli_DRI_45 EQU (0x00A)
xlli_DRI_52 EQU (0x00B) ; 52 MHz setting
xlli_DRI_58 EQU (0x00D)
xlli_DRI_65 EQU (0x00E) ; 65 MHz setting
xlli_DRI_68 EQU (0x00F)
xlli_DRI_71 EQU (0x010) ; 71 MHz setting
xlli_DRI_74 EQU (0x011)
xlli_DRI_78 EQU (0x012) ; 78 MHz setting
xlli_DRI_81 EQU (0x012)
xlli_DRI_84 EQU (0x013) ; 84 MHz setting
xlli_DRI_87 EQU (0x014)
xlli_DRI_91 EQU (0x015) ; 91 MHz setting
xlli_DRI_94 EQU (0x016) ; 94 MHz setting
xlli_DRI_97 EQU (0x016) ; 97 MHz setting
xlli_DRI_100 EQU (0x017) ; 100 MHz setting
xlli_DRI_104 EQU (0x018) ; 104 MHz setting
xlli_DRI_110 EQU (0x01A)
xlli_DRI_117 EQU (0x01B) ; 117 MHz setting
xlli_DRI_124 EQU (0x01D)
xlli_DRI_130 EQU (0x01E) ; 130 MHz setting
xlli_DRI_136 EQU (0x020)
xlli_DRI_143 EQU (0x021)
xlli_DRI_149 EQU (0x023)
xlli_DRI_156 EQU (0x025)
xlli_DRI_162 EQU (0x026)
xlli_DRI_169 EQU (0x028) ; 169 MHz setting
xlli_DRI_175 EQU (0x029)
xlli_DRI_182 EQU (0x02B)
xlli_DRI_188 EQU (0x02D)
xlli_DRI_195 EQU (0x02E)
xlli_DRI_201 EQU (0x030)
xlli_DRI_208 EQU (0x031) ; 208 MHz setting
; SDRAM Settings
xlli_MDCNFG_value EQU (0x00000AC8) ; SDRAM Config Reg
xlli_MDMRS_value EQU (0x00000000) ; SDRAM Mode Reg Set Config Reg
;
; MEMORY PHYSICAL BASE ADDRESS(S)
;
xlli_SRAM_PHYSICAL_BASE EQU (0X5C000000) ; Physical base address for SRAM
xlli_SDRAM_PHYSICAL_BASE EQU (0xA0000000) ; Physical base address for SDRAM
;
; CORE, SYSTEM BUS, MEMORY BUS Default frequency setting for Mainstone
;
xlli_CCCR_value EQU (0x00000107) ; Bulverde (HW reset value to start)
;
; Clock Enable Register (CKEN) setting
;
xlli_CKEN_value EQU (0x00400200) ; Data to be set into the clock enable register
; bit 9 enables OS timers
; Bit 22 enables memory clock
;
; Address where system configuration data is stored
;
xlli_SCR_data EQU (0x5C03FFFC) ; Address in SRAM where system config data is stored
;
; Misc constants
;
xlli_MemSize_1Mb EQU (0x00100000)
xlli_p_PageTable EQU (0xA3FFC000) ; Base address for memory Page Table
xlli_s_PageTable EQU (0x00004000) ; Page Table size (4K words - 16 Kb)
IF :DEF: POST_BUILD
xlli_v_xbBOOTROM EQU (0x04000000) ; (0x04000000 for POST)
ELSE
xlli_v_xbBOOTROM EQU (0x00000000)
ENDIF;
END
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