bvd1bd.inc

Xcale270Bsp包,wince平台

GAFR0_U_VAL EQU  (0xA5E54018)
GAFR1_L_VAL EQU  (0x999A955A)
GAFR1_U_VAL EQU  (0xAAA5A0AA)
GAFR2_L_VAL EQU  (0xAAAAAAAA)
GAFR2_U_VAL EQU  (0x55F0A402)
GAFR3_L_VAL EQU  (0x540A950C)
GAFR3_U_VAL EQU  (0x00001599)

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;       
;;;;;   MAINSTONE BASEBOARD REGISTER (FPGA) values
;;;;;
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; Hex LED Initial Settings
;
HEXLED1_VAL             EQU     0x00000000    ; Zero-out LEDs
HEXLED2_VAL             EQU     0x0000FF3F    ; Turn off decimals and other dots on the HEX LEDs.
LEDCTL_ALL              EQU     0x000000FF    ; HEX LEDs ON, all discretes off.

; MISC_WR Initial Settings
;
MISCWR1_VAL             EQU     0x00000020    ; everything off, PCMCIA/BB Mux: route signals to PCMCIA.
MISCWR2_VAL             EQU     0x00000010    ; everything off including USB client detection

; INT register Initial Settings
;
INTMSKEN1_VAL           EQU     0x00000000    ; mask all ints
INTSETCLR1_VAL          EQU     0x00000000    ; clear all ints



;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;       
;;;;;   MAINSTONE VIRTUAL CONFIG REGISTERS (GPIOx) values
;;;;;
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; SCR Masks & Constants.  *The SCR is not a register: it is the result of reading GPIO[73:58] before assigning an alternate function to them.
;   Therefore, these constants can be used once this value is is read, masked correctly and stored off to driver globals.
;
SCR_SWAP_FLASH_MASK     EQU     (0x1 << 15)
SCR_EXBID_MASK          EQU     (0x3 << 13)
SCR_nEXB_PRES_MASK      EQU     (0x1 << 12)
SCR_MBREV_MASK          EQU     (0x7 << 9)
SCR_nMBPRES_MASK        EQU     (0x1 << 8)
SCR_DCREV_MASK          EQU     (0x7 << 5)
SCR_DCID_MASK           EQU     (0xF)

SCR_MBREV_1p0           EQU     0x0           ; Main Board Revision 1.0
SCR_MBREV_1p1           EQU     0x1           ; Main Board Revision 1.1
SCR_DCREV_1p0           EQU     0x0           ; Daughter Card Revision 1.0
SCR_DCREV_1p1           EQU     0x1           ; Daughter Card Revision 1.1

; LCDCR Masks & Constants *The SCR is not a register: it is the result of reading GPIO[87,86,77,75,74,19,14] before assigning an alternate function to them.
;
LCDCR_ORIENT_MASK       EQU     (0x1 << 6)
LCDCR_LCDID_MASK        EQU     (0x3F)

LCDCR_ORIENT_LANDSCAPE               EQU     0x1
LCDCR_LCDID_TOSHIBA_LTM04C380K_V18   EQU     0X1    ; 256 KB
LCDCR_LCDID_TOSHIBA_LTM04C380K_V16   EQU     0      ; 64 KB




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;;;;;       
;;;;;   MAINSTONE BASEBOARD REGISTER MASKS
;;;;;
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; GP Switches
;
SW12_MASK               EQU     (0x1 << 15)
SW11_MASK               EQU     (0x1 << 14)
SW10_MASK               EQU     (0x1 << 13)
SW8_MASK                EQU     (0x1 << 12)
SW7_MASK                EQU     (0x1 << 11)
SW6_MASK                EQU     (0x1 << 10)
SW4_MASK                EQU     (0x1 << 9)
SW3_MASK                EQU     (0x1 << 8)
HEXSW5_MASK             EQU     (0xF << 4)
HEXSW9_MASK             EQU     (0xF)




    
;<bman STOPPED HERE>






; -----------------------------------------------------------------------------
; -----------------------------------------------------------------------------
;
; Processor stepping Values
;

BULVERDE_CP15_A0_VAL  EQU (0x69054110)
BULVERDE_CP15_A1_VAL  EQU (0x69054111)
BULVERDE_CP15_B0_VAL  EQU (0x69054112)

BULVERDE_JTAG_A0_VAL  EQU (0x09265013)
BULVERDE_JTAG_A1_VAL  EQU (0x19265013)
BULVERDE_JTAG_B0_VAL  EQU (0x29265013)

A0_STEPPING          EQU (0x0)
A1_STEPPING          EQU (0x1)
B0_STEPPING          EQU (0x2)

;
;  Driver Globals definitions
    IF :DEF: MMXIP_MEMMAP
MEM_BASE_PHYSICAL       EQU  (0xA3A00000) ; A000 0000 + 3A0 0000
    ELSE
MEM_BASE_PHYSICAL       EQU  (0xA3C8D000)
    ENDIF ;MMXIP_MEMMAP

    IF :DEF: MMXIP_MEMMAP
DRIVER_GLOBALS_OFFSET   EQU  (0x2BB000)
    ELSE
DRIVER_GLOBALS_OFFSET   EQU  (0xB000)
    ENDIF ;MMXIP_MEMMAP


TOUCH_GLOBALS_OFFSET        EQU (0x0)
PCMCIA_GLOBALS_OFFSET       EQU (0x100)
PROFILE_GLOBALS_OFFSET      EQU (0x200)
MISC_GLOBALS_OFFSET         EQU (0x300)
PMU_GLOBALS_OFFSET          EQU (0x400)
AC97_GLOBALS_OFFSET         EQU (0x500)
UNINIT_MISC_GLOBALS_OFFSET  EQU (0x800)
DBG_ETH_GLOBALS_OFFSET      EQU (0x900)

DRIVER_GLOBALS_PHYSICAL     EQU    (MEM_BASE_PHYSICAL + DRIVER_GLOBALS_OFFSET)
DRIVER_GLOBALS_CPUID_PHY    EQU    (DRIVER_GLOBALS_PHYSICAL + UNINIT_MISC_GLOBALS_OFFSET)

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;  Sleep Data area definitions
;

; Must keep in synch with MEMDefs.h and config.bib

    IF :DEF: MMXIP_MEMMAP
SLEEP_SAVE_OFFSET           EQU 0x2BA000
    ELSE
SLEEP_SAVE_OFFSET           EQU 0xA000
    ENDIF ;MMXIP_MEMMAP

SLEEP_SAVE_BYTES            EQU 0x1000      ; total size of sleep save area
SLEEP_SAVE_PHYSICAL_BASE    EQU (MEM_BASE_PHYSICAL + SLEEP_SAVE_OFFSET)

; Working backward from end.  All 4-byte data elements.
SLEEP_TYPE_OFFSET               EQU (SLEEP_SAVE_BYTES-4)
RESET_LAUNCH_ADDR_OFFSET        EQU (SLEEP_TYPE_OFFSET-4)        
RESET_OEM_ADDR_TABLE_PA_OFFSET  EQU (RESET_LAUNCH_ADDR_OFFSET-4)
RESET_KERNEL_START_PA_OFFSET    EQU (RESET_OEM_ADDR_TABLE_PA_OFFSET-4)

RESET_LAUNCH_ADDR_PHYSICAL      EQU  (SLEEP_SAVE_PHYSICAL_BASE + RESET_LAUNCH_ADDR_OFFSET)
SLEEP_TYPE_PHYSICAL             EQU  (SLEEP_SAVE_PHYSICAL_BASE + SLEEP_TYPE_OFFSET)

; Define SLEEP TYPES and related constants here

    ; Normal sleep with standard resume desired is standard
    ; Use 0 as basic mode for simplicity, because this area is zero-initialized
    ;   at power up.
SLEEP_TYPE_STANDARD         EQU  0  
SLEEP_TYPE_SOFT_RESET       EQU  1  
;SLEEP_TYPE_ETHDBG_PART_INIT EQU  2

;
;  End Sleep Data area definitions
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

    ; //////////////////////////////////////////////////////////////////////    
    ; This macro compares the CPU ID located in Driver Globals against a given
    ; CPU ID Value

    MACRO
    IsA0CPUID $w1, $w2
        ldr $w1, =DRIVER_GLOBALS_CPU_ID_LOCATION
        ldr $w2, [$w1]    ; Start of driver globals misc section
        ldr $w1, =BULVERDE_CP15_A0_VAL
        cmp $w1, $w2
    MEND

    MACRO
    IsA1CPUID $w1, $w2
        ldr $w1, =DRIVER_GLOBALS_CPU_ID_LOCATION
        ldr $w2, [$w1]    ; Start of driver globals misc section
        ldr $w1, =BULVERDE_CP15_A1_VAL
        cmp $w1, $w2
    MEND

    MACRO
    IsB0CPUID $w1, $w2
        ldr $w1, =DRIVER_GLOBALS_CPU_ID_LOCATION
        ldr $w2, [$w1]    ; Start of driver globals misc section
        ldr $w1, =BULVERDE_CP15_B0_VAL
        cmp $w1, $w2
    MEND


    ENDIF
    END