bvd1bd.inc

Xcale270Bsp包,wince平台

;----------------------------------------
;  Copyright ?2002-2003 Intel Corp. 
;
; Assembler logical name header file for Bulverde-Mainstone
;----------------------------------------
    INCLUDE Bvd1.inc
    INCLUDE GPIO.inc    

    IF  !:DEF: Bvd1BD_inc
Bvd1BD_inc  EQU 1


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;;;;;       
;;;;;   MAINSTONE CHIP SELECTS
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;
; Mainstone (on PDC): nCS0: Boot ROM (32MB FLASH)
;
BOOT_FLASH_BASE_PHYSICAL        EQU     0x00000000
    IF :DEF: MMXIP_MEMMAP
BOOT_FLASH_BASE_C_VIRTUAL       EQU     0x80000000
    ELSE
BOOT_FLASH_BASE_C_VIRTUAL       EQU     0x98C00000
    ENDIF ;MMXIP_MEMMAP
BOOT_FLASH_BASE_U_VIRTUAL       EQU     (BOOT_FLASH_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)
    
;
; Mainstone: nCS1: Secondary FLASH (32 MB)
;
SECONDARY_FLASH_BASE_PHYSICAL   EQU     0x04000000
    IF :DEF: MMXIP_MEMMAP
SECONDARY_FLASH_BASE_C_VIRTUAL  EQU     0x82000000
    ELSE
SECONDARY_FLASH_BASE_C_VIRTUAL  EQU     0x96C00000
    ENDIF ;MMXIP_MEMMAP
SECONDARY_FLASH_BASE_U_VIRTUAL  EQU     (SECONDARY_FLASH_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)
;liudiping
    
;
; Mainstone: nCS2: Board-Level Registers (FPGA)
;
FPGA_REGS_BASE_PHYSICAL         EQU     0x08000000
FPGA_REGS_BASE_C_VIRTUAL        EQU     0x96B00000
FPGA_REGS_BASE_U_VIRTUAL        EQU     (FPGA_REGS_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)
    
;
; Mainstone: nCS2 (on PDC): SRAM (2 MB)
;
SRAM_BASE_PHYSICAL              EQU     0x0A000000
SRAM_BASE_C_VIRTUAL             EQU     0x96900000
SRAM_BASE_U_VIRTUAL             EQU     (SRAM_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)

;
; Mainstone: nCS3:  not used, not mapped.  The GPIO is used as PCMCIA PSKTSEK signal on Mainstone.
;
CS3_BASE_PHYSICAL               EQU     0x0C000000
CS3_BASE_C_VIRTUAL              EQU     0x96800000
CS3_BASE_U_VIRTUAL              EQU     (CS3_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)

;
; Mainstone: nCS4: Ethernet (SMSC 91C111)
;
SMSC_ETHERNET_BASE_PHYSICAL     EQU     0x10000000
SMSC_ETHERNET_BASE_C_VIRTUAL    EQU     0x96700000
SMSC_ETHERNET_BASE_U_VIRTUAL    EQU     (SMSC_ETHERNET_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)

;
; Mainstone: nCS5: eXpansion Board Header
;
XDC_BASE_PHYSICAL               EQU     0x14000000
XDC_BASE_C_VIRTUAL              EQU     0x96600000
XDC_BASE_U_VIRTUAL              EQU     (XDC_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)
     


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;;;;;       
;;;;;   MAINSTONE BASEBOARD REGISTER OFFSETS
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;
; Mainstone Platform Registers' offsets from FPGA_REGS_BASE_... (FPGA on lower half of nCS2)
;
LEDDAT1_OFFSET                  EQU     0x00000010          ; Hex LED Data Register 1. (8 LEDS DATA U19 (MSN),21,23,25,18,20,22,24 (LSN)) 
LEDDAT2_OFFSET                  EQU     0x00000014          ; Hex LED Data Register 2. (Decimal points and dots)
LEDCTL_OFFSET                   EQU     0x00000040          ; LED Control (Blanking for HEX LEDs, discrete LED on/off)
GPSW_OFFSET                     EQU     0x00000060          ; General Purpose Switches + HEX Rotaries Status (read-only)        
MISCWR1_OFFSET                  EQU     0x00000080          ; Miscellaneous Write Register 1
MISCWR2_OFFSET                  EQU     0x00000084          ; Miscellaneous Write Register 2
MISCRD_OFFSET                   EQU     0x00000090          ; Miscellaneous Read Register
INTMSKEN1_OFFSET                EQU     0x000000C0          ; Platform Interrupt Mask/Enable 1
INTSETCLR_OFFSET                EQU     0x000000D0          ; Platform Interrupt Set/Clear 1
PCMCIA0SRCR_OFFSET              EQU     0x000000E0          ; PCMCIA Socket 0 Status/Control
PCMCIA1SRCR_OFFSET              EQU     0x000000E4          ; PCMCIA Socket 1 Status/Control



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;;;;;       
;;;;;   MAINSTONE Memory Controller Values
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; SDRAM Settings
;
MDCNFG_VAL  EQU     0x00000AC9              ; SDRAM Config Reg (CL=3, Normal Addressing, 4 Banks, 13 row bits, 9 col bits, 32-bit port width)
;MDCNFG_VAL  EQU     0x000009C9              ; SDRAM Config Reg (*CL=2, Normal Addressing, 4 Banks, 13 row bits, 9 col bits, 32-bit port width) This is fine for SDCLK=65MHz, and is really close for SDCLK=100MHz

MDREFR_VAL  EQU     0x2093A01E              ; SDRAM Refresh Reg (SDCLK[0]=MemClk/4, APD, SDCLK[1]=MemClk/2, DRI=x01E (7.62us refreshes))
;MDREFR_VAL  EQU     0x2093A010              ; SDRAM Refresh Reg (SDCLK[0]=MemClk/4, APD, SDCLK[1]=MemClk/2, DRI=xFFF Most frequent refresh!!!

MDMRS_VAL   EQU     0x00000000              ; SDRAM Mode Reg Set Config Reg (MDMRS1: burst reads & writes)
MDMRSLP_VAL EQU     0x0000C008              ; SDRAM Mode Reg Set Config Reg - Low Power (enabled, 45 C TCR, all banks PASR (partial array self refresh))

; Static Memory Settings
;
K3_MSC0_VAL    EQU    0x39F2A7A3              ; Static Mem. Control Reg 0 (nCS0,1)=(Boot Flash, Secondary Flash)
;MSC0_VAL    EQU     0x39F2CEA3              ; RDN 7-->4  R: no dicey, 2)doubled RDN and RRR R: no dicey
;MSC0_VAL    EQU     0x39F297E3              ; RDN 7-->4  R: no dicey, 2)doubled RDN and RRR R: no dicey, all F's R: better, but copy fails, FFA3 (no RDF adjustment) R:bad, A7C3 (only RDF adjusted) R: yeah!
J3_MSC0_VAL    EQU    0xA7A339F2             ; just reversed K3's

L3_MSC0_VAL    EQU    0xA7A339F2             ; just reversed K3's - Borrowing J3's for ASync. Tyax at the moment


MSC1_VAL    EQU     0x0000A691              ; Static Mem. Control Reg 1 (nCS2,3)=(FPGA/SRAM, unused)
;MSC1_VAL    EQU     0x0000FFF1              ; Static Mem. Control Reg 1 (nCS2,3)=(FPGA/SRAM, unused)  MAX SLOWNESS!!!

MSC2_VAL    EQU     0x0000B884              ; Static Mem. Control Reg 2 (nCS4,5)=(SMSC, expansion header)

; PCMCIA and CF Interfaces
; hzh, nos=1
MECR_VAL    EQU     0x00000000              ; Expansion memory (PCMCIA/CF) Bus Config (NOS=2, card is NOT there)
MCMEM0_VAL  EQU     0x0000C497              ; Card I-face Common Mem Space socket 0 timing config
MCMEM1_VAL  EQU     0x0000C497              ; Card I-face Common Mem Space socket 1 timing config
MCATT0_VAL  EQU     0x0000C497              ; Card I-face Attribute Space socket 0 timing config 
MCATT1_VAL  EQU     0x0000C497              ; Card I-face Attribute Space socket 1 timing config 
MCIO0_VAL   EQU     0x0000C497              ; Card I-face I/O Space socket 0 timing config       
MCIO1_VAL   EQU     0x0000C497              ; Card I-face I/O Space socket 1 timing config       

; Synch. Static Memory: Processor Daughter Card's K18 FLASH is capable of operating synchronously.
;
SXCNFG_VAL  EQU     0x4000600D              ; Synch. Static Mem. Config. Reg. (Burst-of-8 reads, CL=4, SDCLK return latching)

; Alternate Bus Masters - Fly-By-DMA Mode (unused on Mainstone)
;
FLYCNFG_VAL EQU     0x00010001              ; Fly-by-DMA config. reg (==POR: both DVALs active low)



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;;;;;   MAINSTONE GPIO values
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; GPIO Rising-Edge Detect
;
GRER0_VAL               EQU     0x00000000    
GRER1_VAL               EQU     0x00000000
GRER2_VAL               EQU     0x00000000
GRER3_VAL               EQU     0x00000000

; GPIO Falling-Edge Detect: gpio[1:0]
;
GFER0_VAL               EQU     0x00000000    
GFER1_VAL               EQU     0x00000000
GFER2_VAL               EQU     0x00000000
GFER3_VAL               EQU     0x00000000

;YL-PXA27x use below, hzh
;0->Input,1->LAN91C111 IRQ,3->LCDPWREN,4->CAMERA PWRDN,
;9->IDE IRQ,10->NAND nCE,11->Buzzer,12->CIF_D7,13->ext.,14->CS8900 IRQ,15->nCS1
;16->LCD BK,17->CIF_D6,18->nWAIT,19->ST16C550 IRQ,20->DREQ,21->DVAL,22->USBD PULL-UP,23->CIF_MCLK
;24->CIF_FV,25->CIF_LV,26->CIF_PCLK,27->CIF_D0,28->AC97_BCLK,29->AC97_SDI,30->AC97_SDO,31->AC97_SYNC
;32->MMC_CLK,33->nCS5,34->FFRXD,35->FFCTS,36->FFDCD,37->FFDSR,38->FFRI,39->FFTXD
;40->FFDTR,41->FFRTS,42->BTRXD,43->BTTXD,44->BTCTS,45->BTRTS,46->IRRXD,47->IRTXD
;48->nPOE,49->nPWE,50->nPIOR,51->nPIOW,52->VS2,53->BVD2,54->nPCE2,55->nPREG
;56->nPWAIT,57->nIOIS16,58~63->LDD[0~5]
;64~77->LCD,78->nCS2,79->nCS3
;80->nCS4,81->PCMCIA RDY/nIRQ,82->VS1,83->nCD,84->BVD1,85->nPCE1,86->LDD[16],87->LDD[17]
;88->NAND R/nB,89->LED1,90->CIF_D4,91->CIF_D5,92->MMC_DAT0,93~95->KP_DKIN[0~2]
;96->LED4,97->KP_MKIN[3],98->MMC_nCD,99->MMC_WP,100~102->KP_MKIN[0~2],103->KP_MKOUT[0]
;104->KP_MKOUT[1],105->KP_MKOUT[2],106->ext.,107->LED2,108->LED3,109~111->MMC_DAT[1~3]
;112->MMC_CMD,113->AC97_nRST,114->CIF_D1,115->CIF_D3,116->CIF_D2,117->SCL,118->SDA,
;119,120 supported in PXA271,272,273 only!

GPSR0_VAL          EQU   (0x00008408)   ; Set registers
GPSR1_VAL          EQU   (0x004FAB82)
GPSR2_VAL          EQU   (0x0021C000)

GPSR3_VAL          EQU   (0x00000000)
;liudiping for test
;GPSR3_VAL          EQU   (0x00001800)

GPCR0_VAL          EQU   (0x00010810)   ; Clear registers
GPCR1_VAL          EQU   (0x00000000)   ; FFUART related
GPCR2_VAL          EQU   (0x00000000)
GPCR3_VAL          EQU   (0x00000000)

GPDR0_VAL          EQU   (0xC0A18DFC)   ; Direction Registers
GPDR1_VAL          EQU   (0xFCDFAB83)
GPDR2_VAL          EQU   (0x02E1FFFF)
GPDR3_VAL          EQU   (0x00021B81)

GAFR0_L_VAL EQU  (0x82000000)   ; Alternate function registers