📄 bvd1.inc
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; *
; * This macro enables both IRQ and FIQ nondestructively
; ********************************************************************
MACRO
EnableInts $gp1
MRS $gp1, cpsr ; Get value of CPSR
AND $gp1, $gp1, #IrqFiqEnable ; Set enable/disable bits
MSR cpsr_c, $gp1 ; Control the IRQ/FIQ
MEND
; **** Macro SCRUB_SDRAM *********************************************
; * Params: $StartAdx: 32-bit aligned start address.
; * $NumMB : Number of MB to clear.
; * $gp1,2 : general purpose scratch
; *
; * Returns: nothing
; *
; * Effects: corrupts $gp1,2
; *
; * This macro simply zeros out RAM, ending at $StartAdx, and
; * starting at ($StartAdx + ($NumMB*0x100000)), inclusive. It is the resposibility of the
; * caller to ensure that the addresses are valid! Ensure $StartAdx
; * is 32-bit aligned, or my math will get hosed. I will not alter
; * the $StartAdx parameter to ensure this alignment!
; *
; Ex:
; ldr r0, =0xA0000000 ; start Adx
; mov r1, #64 ; #MB
;
; SCRUB_SDRAM r0, r1, r2, r3
;
; ********************************************************************
MACRO
SCRUB_SDRAM $StartAdx, $NumMB, $gp1, $gp2
;
; Determine ending address: endAdx = (($NumMB * 0x0010 0000) + $StartAdx)
;
mov $gp1, #0x100000
mla $gp2, $NumMB, $gp1, $StartAdx
ldr $gp1, =0x00000000 ; source data
10
sub $gp2, $gp2, #4 ; word pre-decrement
str $gp1, [$gp2] ; 32-bit zero fill
cmp $gp2, $StartAdx
bne %BT10
MEND
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; *Tuned for 64MB 0 set.
; Assumptions: 64 MB contiguous starting at phy 0xA000_0000
;
MACRO
SCRUB_SDRAM_TUNED_64 $gp1, $gp2, $gp3, $gp4, $gp5, $gp6
mov $gp6, #0 ; data
ldr $gp1, =0xA0000000
ldr $gp2, =0xA0000004
ldr $gp3, =0xA0000008
ldr $gp4, =0xA000000C
mov $gp5, #0x04000000 ; loop counter = 64 MB
10
str $gp6, [$gp1], #+16
str $gp6, [$gp2], #+16
str $gp6, [$gp3], #+16
str $gp6, [$gp4], #+16
subs $gp5, $gp5, #16
bne %BT10
str $gp6, [$gp1] ; get last word
MEND
;
; ////////////////////////////////////////////////
; -- MACRO for XScale CoProcessor Writes --
; ////////////////////////////////////////////////
;
MACRO
CPWAIT $Rd
MRC P15, 0, $Rd, C2, C0, 0 ; arbitrary read of CP15
MOV $Rd, $Rd ; wait for it (foward dependency)
SUB PC, PC, #4 ; branch to next instruction
MEND
; ////////////////////////////////////////////////
; //////////////////////////////////////////////////////////////////////
; ////////////////////// ~~~~ MACROS ~~~~ //////////////////////////////
; //////////////////////////////////////////////////////////////////////
;
; **** Macro InitFFUART *********************************************
; * Params: $FBA (FFUart Base Address )$gp2, $gp3 (scratch regs)
; *
; * Returns: nothing
; *
; * Registers: PReserves $FBA, corrupts the rest
; *
; * This macro inits the FFUART in non-polled, non-FIFO mode at 38400 baud.
; ********************************************************************
MACRO
InitFFUART $FBA, $gp2, $gp3
; Disable UART and disable interrupts
ldr $gp2, =0x0
str $gp2, [$FBA, #0x0c] ; (DLAB OFF)
str $gp2, [$FBA, #0x04] ; IER_DLH = 0x0
; Set baud rate divisor (38400 baud)
ldr $gp2, =0x80
str $gp2, [$FBA, #0x0c] ; (DLAB ON)
ldr $gp2, =0x08;0x18 ; hzh, 115200
str $gp2, [$FBA] ; THR_RBR_DLL = 0x18
ldr $gp2, =0x0
str $gp2, [$FBA, #0x04] ; IER_DLH = 0x0
; Set communications parameters to 8,N,1
ldr $gp2, =0x0
str $gp2, [$FBA, #0x0c] ; (DLAB OFF)
ldr $gp2, =0x3
str $gp2, [$FBA, #0x0c] ; LCR = 0x3
; Clear and enable fifos
ldr $gp2, =0x7
str $gp2, [$FBA, #0x08] ; IIR_FCR = 0x8
; Set polled mode
ldr $gp2, =0x0
str $gp2, [$FBA, #0x04] ; IER_DLH = 0x0
; Set normal UART mode
ldr $gp2, =0x0
str $gp2, [$FBA, #0x10] ; MCR = 0
; Enable UART
ldr $gp2, [$FBA, #0x04] ; $gp2 = IER_DLH
orr $gp2, $gp2, #0x40 ; Set the enable uart bit
str $gp2, [$FBA, #0x04] ;
MEND
;
; **** Macro PrintStr *********************************************
; * Params: $FBA (FFUART Base Address), $pStr (pointer to string), $gp1
; *
; * Returns: nothing
; *
; * Effects: Corrupts $pStr & $gp1, preserves $FBA
; *
; * This macro writes the string pointed to by $pSTr until a '0' is reached.
; ********************************************************************
MACRO
PrintStr $FBA, $pStr, $gp1
10
ldrb $gp1, [$pStr] ; load the first byte
cmp $gp1, #0 ; is it NULL?
beq %FT20 ; if so, let's end now (search forward, this macro only)
IsTBE $FBA, $gp1 ; ensure TBE
ldrb $gp1, [$pStr] ; load the first byte (agin, for now... really need another register)
strb $gp1, [$FBA] ; transmit a byte
add $pStr, $pStr, #1 ; and increment the byte pointer
b %BT10 ; otherwise, keep looping (search backwards, this macro only)
20
MEND
;
; **** Macro PrintReg *********************************************
; * Params: $FBA (FFUART Base Address), $Reg (register to dump), rest gp
; *
; * Returns: nothing
; *
; * Prints a 32-bit register to HTERM via FFUART. Does ASCII conversion.
; *
; *
; ********************************************************************
MACRO
PrintReg $FBA, $Reg, $gp1, $gp2, $gp3
; First, must convert register to ASCII
;
mov $gp1, #28 ; n = 28
99
mov $gp2, $Reg LSR $gp1 ; $gp2 = $Reg >> n
and $gp2, $gp2, #0xF ; mask off irrelevant bits
cmp $gp2, #0x0000000A ; if r1 < 0xA
addlt $gp3, $gp2, #0x30 ; $gp3 = ($gp2 + 0x30) {0x0 -> 0x9}
addge $gp3, $gp2, #0x37 ; $gp3 = ($gp2 + 0x37) {0xA -> 0xF)
; Now just dump the char i just converted
;
IsTBE $FBA, $gp2 ; ensure TBE
strb $gp3, [$FBA] ; transmit
subs $gp1, $gp1, #4 ; n=n-4
bne %BT99
; 0th Iteration
;
mov $gp2, $Reg ; $gp2 = $reg (no need to shift for the LSN)
and $gp2, $gp2, #0xF ; mask off irrelevant bits
cmp $gp2, #0x0000000A ; if r1 < 0xA
addlt $gp3, $gp2, #0x30 ; $gp3 = ($gp2 + 0x30) {0x0 -> 0x9}
addge $gp3, $gp2, #0x37 ; $gp3 = ($gp2 + 0x37) [0xA -> 0xF)
; dump the char i just converted
;
IsTBE $FBA, $gp2 ; ensure TBE
strb $gp3, [$FBA] ; transmit
; Add cr/lf
;
mov $gp1, #0x0A
IsTBE $FBA, $gp2 ; ensure TBE
strb $gp1, [$FBA] ; transmit (LF)
;mov $gp1, #0x0D
;IsTBE $FBA, $gp2 ; ensure TBE
;strb $gp1, [$FBA] ; transmit (CR)
MEND
;
; **** Macro IsTBE *********************************************
; * Params: $FBA (FFUART Base Address), $gp1 (scratch reg)
; *
; * Returns: nothing
; *
; * Effects: Corrupts $gp1, preserves $FBA
; *
; * This macro spins until FFUART.LSR.TEMT gets set, indicating it
; * is ready for data.
; ********************************************************************
MACRO
IsTBE $FBA, $gp1
10
ldr $gp1, [$FBA, #FF_LSR_OFFSET]
ands $gp1, $gp1, #0x40 ; mask all but bit 6, and set Z if result=0 (i.e. if bit not set)
beq %BT10
MEND
; This macro will read the CCSR and return the L value in $retval
; $Base should contain the base address of the CCSR (virtual or phy)
;
MACRO
GET_CCSR_L $retval, $Base, $gp1
; read CCCR's value
ldr $retval, [$Base, #CCSR_OFFSET]
; mask out irrelevant bits
ldr $gp1, =0x1F
and $retval, $retval, $gp1
MEND
; This macro will read the CCSR and return the 2N value in $retval
; $Base should contain the base address of the CCSR (virtual or phy)
;
MACRO
GET_CCSR_2N $retval, $Base, $gp1
; read CCCR's value
ldr $retval, [$Base, #CCSR_OFFSET]
; mask out irrelevant bits
ldr $gp1, =0x780
and $retval, $retval, $gp1
mov $retval, $retval LSR #7
MEND
;------------------------------------------------------------------------
; This macro will read cp14, reg 6 and return its value in $retval
;
MACRO
GET_CLKCFG $retval
; read CLKCFG's value
mrc p14, 0, $retval, c6, c0, 0
; mask out irrelevant bits
and $retval, $retval, #0xF
MEND
;
; Bits used for the HWConfig Reg (aka PowerManager.ScratchPad)
;
HWConfig_RESET EQU (0x1 :SHL: 0)
HWCONFIG_DEFAULT EQU (0x01155046)
HWConfig_BootromPM EQU (0x1 :SHL: 12)
PAGEMODE_ON EQU (0x1)
;
; Bits used for CP 15
;
CONTROL_MMU EQU 0x00000001
;
; Defs used for the copying of Code into RAM
;
PHYBASE EQU 0xA7000000 ; not clear why we need this offset..
ENDIF ; !:DEF: Bvd1_inc
END
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