📄 bvd1.inc
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IPR15_OFFSET EQU 0x58
IPR16_OFFSET EQU 0x5C
IPR17_OFFSET EQU 0x60
IPR18_OFFSET EQU 0x64
IPR19_OFFSET EQU 0x68
IPR20_OFFSET EQU 0x6C
IPR21_OFFSET EQU 0x70
IPR22_OFFSET EQU 0x74
IPR23_OFFSET EQU 0x78
IPR24_OFFSET EQU 0x7C
IPR25_OFFSET EQU 0x80
IPR26_OFFSET EQU 0x84
IPR27_OFFSET EQU 0x88
IPR28_OFFSET EQU 0x8C
IPR29_OFFSET EQU 0x90
IPR30_OFFSET EQU 0x94
IPR31_OFFSET EQU 0x98
;//
;// GPIO
;//
GPLR0_OFFSET EQU 0x0 ;GPIO pin-level register 31:0
GPLR1_OFFSET EQU 0x4 ;GPIO pin-level register 63:32
GPLR2_OFFSET EQU 0x8 ;GPIO pin-level register 95:64
GPDR0_OFFSET EQU 0xC ;GPIO pin-direction register 31:0
GPDR1_OFFSET EQU 0x10 ;GPIO pin-direction register 63:32
GPDR2_OFFSET EQU 0x14 ;GPIO pin-direction register 95:64
GPSR0_OFFSET EQU 0x18 ;GPIO pin output set register 31:0
GPSR1_OFFSET EQU 0x1C ;GPIO pin output set register 63:32
GPSR2_OFFSET EQU 0x20 ;GPIO pin output set register 95:64
GPCR0_OFFSET EQU 0x24 ;GPIO pin output clear register 31:0
GPCR1_OFFSET EQU 0x28 ;GPIO pin output clear register 63:32
GPCR2_OFFSET EQU 0x2C ;GPIO pin output clear register 95:64
GRER0_OFFSET EQU 0x30 ;GPIO rising edge detect register 31:0
GRER1_OFFSET EQU 0x34 ;GPIO rising edge detect register 63:32
GRER2_OFFSET EQU 0x38 ;GPIO rising edge detect register 95:64
GFER0_OFFSET EQU 0x3C ;GPIO falling edge detect register 31:0
GFER1_OFFSET EQU 0x40 ;GPIO falling edge detect register 63:32
GFER2_OFFSET EQU 0x44 ;GPIO falling edge detect register 95:64
GEDR0_OFFSET EQU 0x48 ;GPIO edge detect status register 31:0
GEDR1_OFFSET EQU 0x4C ;GPIO edge detect status register 63:32
GEDR2_OFFSET EQU 0x50 ;GPIO edge detect status register 95:64
GAFR0_L_OFFSET EQU 0x54 ;GPIO alternate funciton select register 15:0
GAFR0_U_OFFSET EQU 0x58 ;GPIO alternate function select register 31:16
GAFR1_L_OFFSET EQU 0x5C ;GPIO alternate function select register 47:32
GAFR1_U_OFFSET EQU 0x60 ;GPIO alternate function select register 63:48
GAFR2_L_OFFSET EQU 0x64 ;GPIO alternate function select register 79:64
GAFR2_U_OFFSET EQU 0x68 ;GPIO alternate function select register 95:80
GAFR3_L_OFFSET EQU 0x6C ;GPIO alternate function select register 111:96
GAFR3_U_OFFSET EQU 0x70 ;GPIO alternate function select register 120:112
GPLR3_OFFSET EQU 0x100 ;GPIO pin-level register 120:96
GPDR3_OFFSET EQU 0x10C ;GPIO pin-direction register 120:96
GPSR3_OFFSET EQU 0x118 ;GPIO pin output set register 120:96
GPCR3_OFFSET EQU 0x124 ;GPIO pin output clear register 120:96
GRER3_OFFSET EQU 0x130 ;GPIO rising edge detect register 120:96
GFER3_OFFSET EQU 0x13C ;GPIO falling edge detect register 120:96
GEDR3_OFFSET EQU 0x148 ;GPIO edge detect status register 120:96
;//
;// POWER MANAGER & RESET CONTROLLER
;//
PMCR_OFFSET EQU 0x0 ;Power manager control register
PSSR_OFFSET EQU 0x4 ;Power manager sleep status register
PSPR_OFFSET EQU 0x8 ;Power manager scratch pad register
PWER_OFFSET EQU 0xC ;Power manager wake-up enable register
PRER_OFFSET EQU 0x10 ;Power manager GPIO rising edge detect enable register
PFER_OFFSET EQU 0x14 ;Power manager GPIO falling edge detect enable register
PEDR_OFFSET EQU 0x18 ;Power manager GPIO edge detect status register
PCFR_OFFSET EQU 0x1C ;Power manager general configuration register
PGSR0_OFFSET EQU 0x20 ;Power manager GPIO sleep state register for GPIO 31:0
PGSR1_OFFSET EQU 0x24 ;Power manager GPIO sleep state register for GPIO 63:32
PGSR2_OFFSET EQU 0x28 ;Power manager GPIO sleep state register for GPIO 95:64
PGSR3_OFFSET EQU 0x2C ;Power manager GPIO sleep state register for GPIO 120:96
RCSR_OFFSET EQU 0x30 ; **Reset controller status register**
PSLR_OFFSET EQU 0x34 ;Power manager Sleep Mode Config
PSTR_OFFSET EQU 0x38 ;Power manager Standby Mode Config
PSNR_OFFSET EQU 0x3C ;Power manager Sense Mode Config
PVCR_OFFSET EQU 0x40 ;Power manager Voltage Change Control
PCMD0_OFFSET EQU 0x80 ;Power manager I2C Command[31:0]
PCMD1_OFFSET EQU 0x84
PCMD2_OFFSET EQU 0x88
PCMD3_OFFSET EQU 0x8C
PCMD4_OFFSET EQU 0x90
PCMD5_OFFSET EQU 0x94
PCMD6_OFFSET EQU 0x98
PCMD7_OFFSET EQU 0x9C
PCMD8_OFFSET EQU 0xA0
PCMD9_OFFSET EQU 0xA4
PCMD10_OFFSET EQU 0xA8
PCMD11_OFFSET EQU 0xAC
PCMD12_OFFSET EQU 0xB0
PCMD13_OFFSET EQU 0xB4
PCMD14_OFFSET EQU 0xB8
PCMD15_OFFSET EQU 0xBC
PCMD16_OFFSET EQU 0xC0
PCMD17_OFFSET EQU 0xC4
PCMD18_OFFSET EQU 0xC8
PCMD19_OFFSET EQU 0xCC
PCMD20_OFFSET EQU 0xD0
PCMD21_OFFSET EQU 0xD4
PCMD22_OFFSET EQU 0xD8
PCMD23_OFFSET EQU 0xDC
PCMD24_OFFSET EQU 0xE0
PCMD25_OFFSET EQU 0xE4
PCMD26_OFFSET EQU 0xE8
PCMD27_OFFSET EQU 0xEC
PCMD28_OFFSET EQU 0xF0
PCMD29_OFFSET EQU 0xF4
PCMD30_OFFSET EQU 0xF8
PCMD31_OFFSET EQU 0xFC
PIBMR_OFFSET EQU 0x180 ;Power manager I2C Bus Monitor
PIDBR_OFFSET EQU 0x188 ;Power manager I2C Data Buffer
PI2CR_OFFSET EQU 0x190 ;Power manager I2C Control
PISR_OFFSET EQU 0x198 ;Power manager I2C Status
PISAR_OFFSET EQU 0x1A0 ;Power manager I2C Slave Address
;//
;// CLK MAN
;//
CCCR_OFFSET EQU 0x0 ;Core Clock Configuration Register
CKEN_OFFSET EQU 0x4 ;Clock Enable Register
OSCC_OFFSET EQU 0x8 ;Oscillator Configuration Register
CCSR_OFFSET EQU 0xC ;Core Clock Status
; /////////////////////////////////////////////////////////////////////////////////////////
; /* Peripheral-specific base addresses */
; /////////////////////////////////////////////////////////////////////////////////////////
FFUART_BASE_PHYSICAL EQU (PERIF_BASE_PHYSICAL + FFUART_OFFSET)
FFUART_BASE_C_VIRTUAL EQU (PERIF_BASE_C_VIRTUAL + FFUART_OFFSET)
FFUART_BASE_U_VIRTUAL EQU (PERIF_BASE_U_VIRTUAL + FFUART_OFFSET)
BTUART_BASE_PHYSICAL EQU (PERIF_BASE_PHYSICAL + BTUART_OFFSET)
BTUART_BASE_C_VIRTUAL EQU (PERIF_BASE_C_VIRTUAL + BTUART_OFFSET)
BTUART_BASE_U_VIRTUAL EQU (PERIF_BASE_U_VIRTUAL + BTUART_OFFSET)
STUART_BASE_PHYSICAL EQU (PERIF_BASE_PHYSICAL + STUART_OFFSET)
STUART_BASE_C_VIRTUAL EQU (PERIF_BASE_C_VIRTUAL + STUART_OFFSET)
STUART_BASE_U_VIRTUAL EQU (PERIF_BASE_U_VIRTUAL + STUART_OFFSET)
RTC_BASE_PHYSICAL EQU (PERIF_BASE_PHYSICAL + RTC_OFFSET)
RTC_BASE_C_VIRTUAL EQU (PERIF_BASE_C_VIRTUAL + RTC_OFFSET)
RTC_BASE_U_VIRTUAL EQU (PERIF_BASE_U_VIRTUAL + RTC_OFFSET)
OST_BASE_PHYSICAL EQU (PERIF_BASE_PHYSICAL + OST_OFFSET)
OST_BASE_C_VIRTUAL EQU (PERIF_BASE_C_VIRTUAL + OST_OFFSET)
OST_BASE_U_VIRTUAL EQU (PERIF_BASE_U_VIRTUAL + OST_OFFSET)
INTC_BASE_PHYSICAL EQU (PERIF_BASE_PHYSICAL + INTC_OFFSET)
INTC_BASE_C_VIRTUAL EQU (PERIF_BASE_C_VIRTUAL + INTC_OFFSET)
INTC_BASE_U_VIRTUAL EQU (PERIF_BASE_U_VIRTUAL + INTC_OFFSET)
GPIO_BASE_PHYSICAL EQU (PERIF_BASE_PHYSICAL + GPIO_OFFSET)
GPIO_BASE_C_VIRTUAL EQU (PERIF_BASE_C_VIRTUAL + GPIO_OFFSET)
GPIO_BASE_U_VIRTUAL EQU (PERIF_BASE_U_VIRTUAL + GPIO_OFFSET)
PWR_BASE_PHYSICAL EQU (PERIF_BASE_PHYSICAL + PWR_OFFSET)
PWR_BASE_C_VIRTUAL EQU (PERIF_BASE_C_VIRTUAL + PWR_OFFSET)
PWR_BASE_U_VIRTUAL EQU (PERIF_BASE_U_VIRTUAL + PWR_OFFSET)
CLK_BASE_PHYSICAL EQU (PERIF_BASE_PHYSICAL + CLK_OFFSET)
CLK_BASE_C_VIRTUAL EQU (PERIF_BASE_C_VIRTUAL + CLK_OFFSET)
CLK_BASE_U_VIRTUAL EQU (PERIF_BASE_U_VIRTUAL + CLK_OFFSET)
RCSR_ALL EQU 0x1F ; bman: EAS 1.5 is a bit unclear; is bit 4 reserved or not? If so, then this value should be 0xF
Mode_SVC EQU 0x13
Mode_USR EQU 0x10
NoIntsMask EQU 0x000000C0
IRQIntsMask EQU 0x7F ; 0=enabled, 1=disabled
IrqFiqEnable EQU 0xFFFFFF3F
;
; FLASH constants
;
K3_128Mb_DEVCODE EQU 0x8806
J3_128Mb_DEVCODE EQU 0x18
L3_128Mb_DEVCODE EQU 0x880C
;
; Reset Controller Status Register bit defines
;
RCSR_HARD_RESET EQU (0x1)
RCSR_WDOG_RESET EQU (0x1 << 1)
RCSR_SLEEP_RESET EQU (0x1 << 2)
RCSR_GPIO_RESET EQU (0x1 << 3)
PSSR_VALID_MASK EQU (0x3F)
PSSR_RDH EQU (0x1 << 5)
PSSR_PH EQU (0x1 << 4)
;
; Clock Manager Defs
;
OSCC_OOK EQU (0x1)
OSCC_OON EQU (0x1 << 1)
OSCC_TOUT_EN EQU (0x1 << 2)
OSCC_PIO_EN EQU (0x1 << 3)
OSCC_CRI EQU (0x1 << 4)
CKEN_DEFAULT EQU 0x004002C0 ; MEMC, OST, BTUART clocked. Rest OFF, hzh
;
; Power Manager Defs
;
PCFR_OPDE EQU (0x1)
PCFR_FP EQU (0x1 << 1)
PCFR_FS EQU (0x1 << 2)
PCFR_GPR_EN EQU (0x1 << 4)
PCFR_SYSEN_EN EQU (0x1 << 5)
PCFR_PI2C_EN EQU (0x1 << 6)
PCFR_DC_EN EQU (0x1 << 7)
PCFR_FVC EQU (0x1 << 10)
PCFR_L1_EN EQU (0x1 << 11)
PCFR_GP_ROD EQU (0x1 << 12)
PWER_WE0 EQU (0x1)
PWER_WE1 EQU (0x1 << 1)
PWER_WBB EQU (0x1 << 25)
PWER_WEUSBC EQU (0x1 << 26)
PWER_WEUSBH0 EQU (0x1 << 27)
PWER_WEUSBH1 EQU (0x1 << 28)
PWER_WEP1 EQU (0x1 << 30)
PWER_WERTC EQU (0x1 << 31)
PMCR_BIDAE EQU (0x1)
PMCR_BIDAS EQU (0x1 << 1)
PMCR_VIDAE EQU (0x1 << 2)
PMCR_VIDAS EQU (0x1 << 3)
PMCR_IAS EQU (0x1 << 4)
PMCR_INTRS EQU (0x1 << 5)
;
; Defs used for Eboot portion of fwBvd1.s
;
EbootOffset EQU 0x00078000 ; comes from BOOT.BIB! Is the offset into EBOOT_PARTITION
EBootImageLen EQU 0x00040000 ; From BOOT.BIB, size field
StackOffset EQU 0x00068000
; bman: get rid of these...
;
BIT0 EQU (1 :SHL: 0)
BIT1 EQU (1 :SHL: 1)
BIT2 EQU (1 :SHL: 2)
BIT3 EQU (1 :SHL: 3)
BIT4 EQU (1 :SHL: 4)
BIT5 EQU (1 :SHL: 5)
BIT6 EQU (1 :SHL: 6)
BIT7 EQU (1 :SHL: 7)
BIT8 EQU (1 :SHL: 8)
BIT9 EQU (1 :SHL: 9)
BIT10 EQU (1 :SHL: 10)
BIT11 EQU (1 :SHL: 11)
BIT12 EQU (1 :SHL: 12)
BIT13 EQU (1 :SHL: 13)
BIT14 EQU (1 :SHL: 14)
BIT15 EQU (1 :SHL: 15)
BIT16 EQU (1 :SHL: 16)
BIT17 EQU (1 :SHL: 17)
BIT18 EQU (1 :SHL: 18)
BIT19 EQU (1 :SHL: 19)
BIT20 EQU (1 :SHL: 20)
BIT21 EQU (1 :SHL: 21)
BIT22 EQU (1 :SHL: 22)
BIT23 EQU (1 :SHL: 23)
BIT24 EQU (1 :SHL: 24)
BIT25 EQU (1 :SHL: 25)
BIT26 EQU (1 :SHL: 26)
BIT27 EQU (1 :SHL: 27)
BIT28 EQU (1 :SHL: 28)
BIT29 EQU (1 :SHL: 29)
BIT30 EQU (1 :SHL: 30)
BIT31 EQU (1 :SHL: 31)
;
; Bits used for Memory Controller Init
;
; register bit masks - mdcnfg
MDCNFG_DE0 EQU (BIT0)
MDCNFG_DE1 EQU (BIT1)
MDCNFG_DWID0 EQU (BIT2)
MDCNFG_DCAC0 EQU (BIT3+BIT4)
MDCNFG_DRAC0 EQU (BIT5+BIT6)
MDCNFG_DNB0 EQU (BIT7)
MDCNFG_DTC0 EQU (BIT8+BIT9)
MDCNFG_DADDR0 EQU (BIT10)
MDCNFG_DLATCH0 EQU (BIT11)
MDCNFG_RESERVED0 EQU (BIT12+BIT13+BIT14+BIT15)
MDCNFG_DE2 EQU (BIT16)
MDCNFG_DE3 EQU (BIT17)
MDCNFG_DWID2 EQU (BIT18)
MDCNFG_DCAC2 EQU (BIT19+BIT20)
MDCNFG_DRAC2 EQU (BIT21+BIT22)
MDCNFG_DNB2 EQU (BIT23)
MDCNFG_DTC2 EQU (BIT24+BIT25)
MDCNFG_DADDR2 EQU (BIT26)
MDCNFG_DLATCH2 EQU (BIT27)
MDCNFG_RESERVED2 EQU (BIT28+BIT29+BIT30+BIT31)
MDREFR_E0PIN EQU 0x00001000
MDREFR_K0RUN EQU 0x00002000
MDREFR_K1RUN EQU 0x00010000
MDREFR_K2RUN EQU 0x00040000
MDREFR_SLFRSH EQU 0x00400000
MDREFR_E1PIN EQU 0x00008000
MDREFR_K1DB2 EQU 0x00020000 ; run SDCLK[1] @ .5(MClk)
MDREFR_K0DB2 EQU 0x00004000
MDREFR_K0DB4 EQU 0x20000000 ; run SDCLK[0] @ .25(MemClk)
MDREFR_K0FREE EQU 0x00800000
MDREFR_K1FREE EQU 0x01000000
MDREFR_K2FREE EQU 0x02000000
MDREFR_APD EQU 0x00100000
BANK_SHIFT EQU 20
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
; MACROS
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
; **** Macro DisableInts *********************************************
; * Params: $gp1 (scratch reg)
; *
; * Returns: nothing
; *
; * This macro disables both IRQ and FIQ nondestructively
; ********************************************************************
MACRO
DisableInts $gp1
MRS $gp1, cpsr ; Get value of CPSR
ORR $gp1, $gp1, #NoIntsMask ; Set IRQ and FIQ-disabling bits
MSR cpsr_c, $gp1 ; Disable the IRQ/FIQ
MEND
;
; **** Macro EnableInts *********************************************
; * Params: $gp1 (scratch reg)
; *
; * Returns: nothing
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