📄 bvd1.inc
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; Copyright ?2002-2003 Intel Corp.
; Bulverde Definitions
;
IF !:DEF: Bvd1_inc
Bvd1_inc EQU 1
CACHED_TO_UNCACHED_OFFSET EQU 0x20000000
; ////////////////////////////////////////////////////
; /* DEVICE BASE ADDRESSES GROUPED BY FUNCTIONALITY */
; ////////////////////////////////////////////////////
;
; SDRAM
; *We Split SDRAM; lower for EBOOT, the rest for WinCE
;
SDRAM_BASE_PHYSICAL EQU 0xA0000000
IF :DEF: MMXIP_MEMMAP
SDRAM_BASE_C_VIRTUAL EQU 0x96C00000
ELSE
SDRAM_BASE_C_VIRTUAL EQU 0x80000000
ENDIF ;MMXIP_MEMMAP
SDRAM_BASE_U_VIRTUAL EQU (SDRAM_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)
EBOOT_TO_WINCE_PARTITION_OFFSET EQU 0x0008D000
;
; Define EBOOT's logical partition
;
SDRAM_PHY_EBOOT_PARTITION EQU SDRAM_BASE_PHYSICAL
SDRAM_VIR_C_EBOOT_PARTITION EQU (SDRAM_BASE_C_VIRTUAL)
SDRAM_VIR_U_EBOOT_PARTITION EQU (SDRAM_VIR_C_EBOOT_PARTITION + CACHED_TO_UNCACHED_OFFSET)
;
; Define WinCE's logical partition
;
SDRAM_PHY_WINCE_PARTITION EQU (SDRAM_PHY_EBOOT_PARTITION + EBOOT_TO_WINCE_PARTITION_OFFSET)
SDRAM_VIR_C_WINCE_PARTITION EQU (SDRAM_VIR_C_EBOOT_PARTITION + EBOOT_TO_WINCE_PARTITION_OFFSET)
SDRAM_VIR_U_WINCE_PARTITION EQU (SDRAM_VIR_C_WINCE_PARTITION + CACHED_TO_UNCACHED_OFFSET)
;
; Define Cache Flag address *NOTE: MUST be kept in sync with config.bib
;
IF :DEF: MMXIP_MEMMAP
CACHE_FLG EQU 0x9A8BC000
ELSE
CACHE_FLG EQU 0x83CC4000
ENDIF ;MMXIP_MEMMAP
; // ZERO-BANK Note: Bulverde Does NOT provide us with an actual Zero-Bank;
; // instead, we will use this address for dcache flushing, which does not
; // require Phy mem to actually exist (see FlushDCache() )
ZBANK_BASE_PHYSICAL EQU 0xE0000000
ZBANK_BASE_C_VIRTUAL EQU 0x96500000 ; cached virtual
ZBANK_BASE_U_VIRTUAL EQU (ZBANK_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)
;
; Internal Memory - Storage (256 KB)
;
IM_STORAGE_BASE_PHYSICAL EQU 0x5C000000
IM_STORAGE_BASE_C_VIRTUAL EQU 0x84000000
IM_STORAGE_BASE_U_VIRTUAL EQU (IM_STORAGE_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)
;
; Internal Memory - Control (12 B)
;
IM_CONTROL_BASE_PHYSICAL EQU 0x58000000
IM_CONTROL_BASE_C_VIRTUAL EQU 0x84100000
IM_CONTROL_BASE_U_VIRTUAL EQU (IM_CONTROL_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)
;
; Camera Peripheral
;
CMRA_BASE_PHYSICAL EQU 0x50000000
CMRA_BASE_C_VIRTUAL EQU 0x9AC00000
CMRA_BASE_U_VIRTUAL EQU (CMRA_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)
;
; USB Host
;
USBH_BASE_PHYSICAL EQU 0x4C000000
USBH_BASE_C_VIRTUAL EQU 0x84200000
USBH_BASE_U_VIRTUAL EQU (USBH_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)
;
; MEMC
;
MEMC_BASE_PHYSICAL EQU 0x48000000
MEMC_BASE_C_VIRTUAL EQU 0x84300000 ; cached virtual
MEMC_BASE_U_VIRTUAL EQU (MEMC_BASE_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET)
;
; LCDC
;
LCD_BASE_PHYSICAL EQU 0x44000000
LCD_BASE_C_VIRTUAL EQU 0x84400000
LCD_BASE_U_VIRTUAL EQU (LCD_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)
;
; perifs - DMAC, UART[3:1/SIR], I2S/C, AC97, USBC, FIR, RTC, OST, PWM, INTC, GPIO, PWRMAN/RESETC, SSP[3:1], MMC, CLKMAN, BB, KYPD, USIM, MEMSTICK
;
PERIF_BASE_PHYSICAL EQU 0x40000000
PERIF_BASE_C_VIRTUAL EQU 0x84500000 ; cached virtual
PERIF_BASE_U_VIRTUAL EQU (PERIF_BASE_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET)
;
; PCMCIA Slots 0,1
;
PCMCIA_S0_IO_PHYSICAL EQU 0x20000000
PCMCIA_S0_IO_C_VIRTUAL EQU 0x94500000 ; cached virtual
PCMCIA_S0_IO_U_VIRTUAL EQU (PCMCIA_S0_IO_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET)
PCMCIA_S0_ATTR_PHYSICAL EQU 0x28000000
PCMCIA_S0_ATTR_C_VIRTUAL EQU 0x92500000 ; cached virtual
PCMCIA_S0_ATTR_U_VIRTUAL EQU (PCMCIA_S0_ATTR_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET)
PCMCIA_S0_CMN_PHYSICAL EQU 0x2C000000
PCMCIA_S0_CMN_C_VIRTUAL EQU 0x8E500000 ; cached virtual
PCMCIA_S0_CMN_U_VIRTUAL EQU (PCMCIA_S0_CMN_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET)
PCMCIA_S1_IO_PHYSICAL EQU 0x30000000
PCMCIA_S1_IO_C_VIRTUAL EQU 0x8C500000 ; cached virtual
PCMCIA_S1_IO_U_VIRTUAL EQU (PCMCIA_S1_IO_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET)
PCMCIA_S1_ATTR_PHYSICAL EQU 0x38000000
PCMCIA_S1_ATTR_C_VIRTUAL EQU 0x8A500000 ; cached virtual
PCMCIA_S1_ATTR_U_VIRTUAL EQU (PCMCIA_S1_ATTR_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET)
PCMCIA_S1_CMN_PHYSICAL EQU 0x3C000000
PCMCIA_S1_CMN_C_VIRTUAL EQU 0x86500000 ; cached virtual
PCMCIA_S1_CMN_U_VIRTUAL EQU (PCMCIA_S1_CMN_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET)
; /////////////////////////////////////////////////////////////////////////////////////////
; /* Peripheral OFFSETS */
; /////////////////////////////////////////////////////////////////////////////////////////
;//
;// mmr-perifs
;//
DMAC_OFFSET EQU 0x0 ; DMA CONTROLLER
FFUART_OFFSET EQU 0x00100000 ; Full-Feature UART
BTUART_OFFSET EQU 0x00200000 ; BlueTooth UART
I2C_OFFSET EQU 0x00300000 ; I2C
I2S_OFFSET EQU 0x00400000 ; I2S
AC97_OFFSET EQU 0x00500000 ; AC97
UDC_OFFSET EQU 0x00600000 ; UDC (usb client)
STUART_OFFSET EQU 0x00700000 ; Standard UART
FIR_OFFSET EQU 0x00800000 ; FIR
RTC_OFFSET EQU 0x00900000 ; real time clock
OST_OFFSET EQU 0x00A00000 ; OS Timer
PWM0_2_OFFSET EQU 0x00B00000 ; PWM 0 (pulse-width mod)
PWM1_3_OFFSET EQU 0x00C00000 ; PWM 1 (pulse-width mod)
INTC_OFFSET EQU 0x00D00000 ; Interrupt controller
GPIO_OFFSET EQU 0x00E00000 ; GPIO
PWR_OFFSET EQU 0x00F00000 ; Power Manager and Reset Control
SSP1_OFFSET EQU 0x01000000 ; SSP 1
MMC_OFFSET EQU 0x01100000 ; MMC
CLK_OFFSET EQU 0x01300000 ; Clock Manager
BB_OFFSET EQU 0x01400000 ; Baseband Interface
KYPD_OFFSET EQU 0x01500000 ; Keypad Interface
USIM_OFFSET EQU 0x01600000 ; USIM
SSP2_OFFSET EQU 0x01700000 ; SSP 2
MEMSTK_OFFSET EQU 0x01800000 ; Memory Stick
SSP3_OFFSET EQU 0x01900000 ; SSP 3
; /////////////////////////////////////////////////////////////////////////////////////////
; /* RELEVANT REGISTER-SPECIFIC OFFSETS */
; /////////////////////////////////////////////////////////////////////////////////////////
;//
;// MEMC
;//
MDCNFG_OFFSET EQU 0x0
MDREFR_OFFSET EQU 0x4
MSC0_OFFSET EQU 0x8
MSC1_OFFSET EQU 0xC
MSC2_OFFSET EQU 0x10
MECR_OFFSET EQU 0x14
SXCNFG_OFFSET EQU 0x1C
FLYCNFG_OFFSET EQU 0x20
MCMEM0_OFFSET EQU 0x28
MCMEM1_OFFSET EQU 0x2C
MCATT0_OFFSET EQU 0x30
MCATT1_OFFSET EQU 0x34
MCIO0_OFFSET EQU 0x38
MCIO1_OFFSET EQU 0x3C
MDMRS_OFFSET EQU 0x40
BOOT_DEF_OFFSET EQU 0x44
ARB_CNTL_OFFSET EQU 0x48
BSCNTR0_OFFSET EQU 0x4C
BSCNTR1_OFFSET EQU 0x50
LCDBSCNTR_OFFSET EQU 0x54
MDMRSLP_OFFSET EQU 0x58
BSCNTR2_OFFSET EQU 0x5C
BSCNTR3_OFFSET EQU 0x60
;//
;// FULL-FEATURE UART
;//
FF_THR_OFFSET EQU 0x0 ;DLAB = 0 WO 8bit - Transmit Holding Register
FF_RBR_OFFSET EQU 0x0 ;DLAB = 0 RO 8bit - Recieve Buffer Register
FF_DLL_OFFSET EQU 0x0 ;DLAB = 1 RW 8bit - Divisor Latch Low Register
FF_IER_OFFSET EQU 0x4 ;DLAB = 0 RW 8bit - Interrupt Enable Register
FF_DLH_OFFSET EQU 0x4 ;DLAB = 1 RW 8bit - Divisor Latch High Register
FF_IIR_OFFSET EQU 0x8 ;DLAB = X RO 8bit - Interrupt Identification Register
FF_FCR_OFFSET EQU 0x8 ;DLAB = X WO 8bit - FIFO Control Register
FF_LCR_OFFSET EQU 0xC ;DLAB = X RW 8bit - Line Control Register
FF_MCR_OFFSET EQU 0x10 ;DLAB = X RW 8bit - Modem Control Regiser
FF_LSR_OFFSET EQU 0x14 ;DLAB = X RO 8bit - Line Status Register
FF_MSR_OFFSET EQU 0x18 ;DLAB = X RO 8bit - Modem Status Register
FF_SPR_OFFSET EQU 0x1C ;DLAB = X RW 8bit - Scratchpad Register
FF_ISR_OFFSET EQU 0x20 ;DLAB = X RW 8bit - Slow Infrared Select Register
FF_FOR_OFFSET EQU 0x24 ;DLAB = X RO FIFO Occupancy Register
FF_ABR_OFFSET EQU 0x28 ;DLAB = X RW Autobaud Control Register
FF_ACR_OFFSET EQU 0x2C ;DLAB = X Autobaud Count Register
;//
;// BLUETOOTH UART
;//
BT_THR_OFFSET EQU 0x0 ;DLAB = 0 WO 8bit - Transmit Holding Register
BT_RBR_OFFSET EQU 0x0 ;DLAB = 0 RO 8bit - Recieve Buffer Register
BT_DLL_OFFSET EQU 0x0 ;DLAB = 1 RW 8bit - Divisor Latch Low Register
BT_IER_OFFSET EQU 0x4 ;DLAB = 0 RW 8bit - Interrupt Enable Register
BT_DLH_OFFSET EQU 0x4 ;DLAB = 1 RW 8bit - Divisor Latch High Register
BT_IIR_OFFSET EQU 0x8 ;DLAB = X RO 8bit - Interrupt Identification Register
BT_FCR_OFFSET EQU 0x8 ;DLAB = X WO 8bit - FIFO Control Register
BT_LCR_OFFSET EQU 0xC ;DLAB = X RW 8bit - Line Control Register
BT_MCR_OFFSET EQU 0x10 ;DLAB = X RW 8bit - Modem Control Regiser
BT_LSR_OFFSET EQU 0x14 ;DLAB = X RO 8bit - Line Status Register
BT_MSR_OFFSET EQU 0x18 ;DLAB = X RO 8bit - Modem Status Register
BT_SPR_OFFSET EQU 0x1C ;DLAB = X RW 8bit - Scratchpad Register
BT_ISR_OFFSET EQU 0x20 ;DLAB = X RW 8bit - Slow Infrared Select Register
BT_FOR_OFFSET EQU 0x24 ;DLAB = X RO FIFO Occupancy Register
BT_ABR_OFFSET EQU 0x28 ;DLAB = X RW Autobaud Control Register
BT_ACR_OFFSET EQU 0x2C ;DLAB = X Autobaud Count Register
;//
;// STANDARD UART
;//
ST_THR_OFFSET EQU 0x0 ;DLAB = 0 WO 8bit - Transmit Holding Register
ST_RBR_OFFSET EQU 0x0 ;DLAB = 0 RO 8bit - Recieve Buffer Register
ST_DLL_OFFSET EQU 0x0 ;DLAB = 1 RW 8bit - Divisor Latch Low Register
ST_IER_OFFSET EQU 0x4 ;DLAB = 0 RW 8bit - Interrupt Enable Register
ST_DLH_OFFSET EQU 0x4 ;DLAB = 1 RW 8bit - Divisor Latch High Register
ST_IIR_OFFSET EQU 0x8 ;DLAB = X RO 8bit - Interrupt Identification Register
ST_FCR_OFFSET EQU 0x8 ;DLAB = X WO 8bit - FIFO Control Register
ST_LCR_OFFSET EQU 0xC ;DLAB = X RW 8bit - Line Control Register
ST_MCR_OFFSET EQU 0x10 ;DLAB = X RW 8bit - Modem Control Regiser
ST_LSR_OFFSET EQU 0x14 ;DLAB = X RO 8bit - Line Status Register
ST_MSR_OFFSET EQU 0x18 ;DLAB = X RO 8bit - Modem Status Register
ST_SPR_OFFSET EQU 0x1C ;DLAB = X RW 8bit - Scratchpad Register
ST_ISR_OFFSET EQU 0x20 ;DLAB = X RW 8bit - Slow Infrared Select Register
ST_FOR_OFFSET EQU 0x24 ;DLAB = X RO FIFO Occupancy Register
ST_ABR_OFFSET EQU 0x28 ;DLAB = X RW Autobaud Control Register
ST_ACR_OFFSET EQU 0x2C ;DLAB = X Autobaud Count Register
;//
;// RTC
;//
RCNR_OFFSET EQU 0x0 ;RTC count register
RTAR_OFFSET EQU 0x4 ;RTC alarm register
RTSR_OFFSET EQU 0x8 ;RTC status register
RTTR_OFFSET EQU 0xC ;RTC timer trim register
RDCR_OFFSET EQU 0x10 ;RTC Day Counter
RYCR_OFFSET EQU 0x14 ;RTC Year Counter
RDAR1_OFFSET EQU 0x18 ;RTC Day Alarm 1
RYAR1_OFFSET EQU 0x1C ;RTC Year Alarm 1
RDAR2_OFFSET EQU 0x20 ;RTC Day Alarm 2
RYAR2_OFFSET EQU 0x24 ;RTC Year Alarm 2
SWCR_OFFSET EQU 0x28 ;RTC Stopwatch Counter
SWAR1_OFFSET EQU 0x2C ;RTC Stopwatch Alarm 1
SWAR2_OFFSET EQU 0x30 ;RTC Stopwatch Alarm 2
PICR_OFFSET EQU 0x34 ;RTC Periodic Interrupt Counter
PIAR_OFFSET EQU 0x38 ;RTC Periodic Interrupt Alarm
;//
;// OST (OS TIMER)
;//
OSMR0_OFFSET EQU 0x0 ;OS timer match register 0
OSMR1_OFFSET EQU 0x4 ;OS timer match register 1
OSMR2_OFFSET EQU 0x8 ;OS timer match register 2
OSMR3_OFFSET EQU 0xC ;OS timer match register 3
OSCR0_OFFSET EQU 0x10 ;OS timer counter register 0
OSSR_OFFSET EQU 0x14 ;OS timer status register
OWER_OFFSET EQU 0x18 ;OS timer watchdog enable register
OIER_OFFSET EQU 0x1C ;OS timer interrupt enable register
OSCR4_OFFSET EQU 0x40
OSCR5_OFFSET EQU 0x44
OSCR6_OFFSET EQU 0x48
OSCR7_OFFSET EQU 0x4C
OSCR8_OFFSET EQU 0x50
OSCR9_OFFSET EQU 0x54
OSCR10_OFFSET EQU 0x58
OSCR11_OFFSET EQU 0x5C
OSMR4_OFFSET EQU 0x80
OSMR5_OFFSET EQU 0x84
OSMR6_OFFSET EQU 0x88
OSMR7_OFFSET EQU 0x8C
OSMR8_OFFSET EQU 0x90
OSMR9_OFFSET EQU 0x94
OSMR10_OFFSET EQU 0x98
OSMR11_OFFSET EQU 0x9C
OMCR4_OFFSET EQU 0xC0
OMCR5_OFFSET EQU 0xC4
OMCR6_OFFSET EQU 0xC8
OMCR7_OFFSET EQU 0xCC
OMCR8_OFFSET EQU 0xD0
OMCR9_OFFSET EQU 0xD4
OMCR10_OFFSET EQU 0xD8
OMCR11_OFFSET EQU 0xDC
;//
;// INTC (INTERRUPT CONTROLLER) - Memory-mapped addresses (can also use c-proc for most of these)
;//
ICIP_OFFSET EQU 0x0 ;Interrupt controller IRQ pending register
ICMR_OFFSET EQU 0x4 ;Interrupt controller mask register
ICLR_OFFSET EQU 0x8 ;Interrupt controller level register
ICFP_OFFSET EQU 0xC ;Interrupt controller FIQ pending register
ICPR_OFFSET EQU 0x10 ;Interrupt controller pending register
ICCR_OFFSET EQU 0x14 ;Interrupt controller control register
ICHP_OFFSET EQU 0x18 ;Interrupt controller Highest Priority register
IPR0_OFFSET EQU 0x1C ;Interrupt controller Priority registerS [31:0]
IPR1_OFFSET EQU 0x20
IPR2_OFFSET EQU 0x24
IPR3_OFFSET EQU 0x28
IPR4_OFFSET EQU 0x2C
IPR5_OFFSET EQU 0x30
IPR6_OFFSET EQU 0x34
IPR7_OFFSET EQU 0x38
IPR8_OFFSET EQU 0x3C
IPR9_OFFSET EQU 0x40
IPR10_OFFSET EQU 0x44
IPR11_OFFSET EQU 0x48
IPR12_OFFSET EQU 0x4C
IPR13_OFFSET EQU 0x50
IPR14_OFFSET EQU 0x54
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