📄 flashfncs.s
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;----------------------------------------------------------------------------------------
;
; INTEL CONFIDENTIAL
; Copyright 2000-2003 Intel Corporation All Rights Reserved.
;
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; Module Name:
;
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; Abstract:
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; Register Useage:
;
;
;----------------------------------------------------------------------------------------
OPT 2 ; disable listing
INCLUDE kxarm.h
INCLUDE Bvd1.inc
INCLUDE Bvd1bd.inc
INCLUDE xlli_Bulverde_defs.inc
INCLUDE xllp_Pm_SleepContext.inc ; Needed for sleep reset processing
;
; Conditional Includes
;
IF BSP_MAINSTONE = "1"
INCLUDE Mainstone.mac
ENDIF
OPT 1 ; reenable listing
EXPORT QUERY_FLASH_CFI
EXPORT GO_SYNC_FLASH
TEXTAREA
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
QUERY_FLASH_CFI
; Query the ROM devices: issue "Read Device Identifier" Command
; L18: 0x880C
; K18: 0x8806
; J3: 0x18
;
; First, enable ICache so that I can take the Flash out of read-array mode safely (MMU of defaults to ICacheable, need MMU on for DCacheability).
; Then, lock the section of code that manipulates the flash into i$.
;
; *16-bit FLASH consideration: I expect the following 32-bit pokes to generate 2 16-bit cycles if 16-bit flash. Would be bad.
; So, options:
; 1) just do single device acesses: so, upper 16 of data on 32-bit writes = 0 ... what does this do on a write if parallel devices?
; 2) handle differently for 16 -vs- 32-bit flash devices? How will MEMC break up?
;
; insert locking code here
add r3, pc, #QUERY_LOCK_START-(.+8)
mvn r0, #31
and r1, r3, r0 ; ensure is 32-byte aligned
add r2, pc, #QUERY_LOCK_END-(.+8)
and r2, r2, r0 ; ensure is 32-byte aligned
mrc p15, 0, r0, c1, c0, 0 ; read (0x78) cp15.1
orr r0, r0, #0x1000 ; enable ICache
mcr p15, 0, r0, c1, c0, 0 ; write it
CPWAIT r0
mcr p15, 0, r0, c9, c1, 1 ; unlock entire i$
mcr p15, 0, r0 ,c7, c5, 0 ; flush i$ and BTB
QUERYLOCKLOOP
mcr p15, 0, r1, c7, c5, 1 ; CYA: invalidate i$ line (same as we are about to lock - CAN affect a locked line!)
mcr p15, 0, r1, c9, c1, 0 ; lock line into icache, based on r1
cmp r1, r2 ; are we done?
add r1, r1, #32 ; increment to next cache-line
bne QUERYLOCKLOOP
IF FLASH_WIDTH_16_BIT = "0" ;If we've got a 32-bit flash bus
;;!!! EV: TODO: MAKE THIS DYNAMIC off BOOTSEL Value!!!!
ALIGN 32 ; ensure is cache-line aligned (i.e. 32 Bytes = 2^5)
QUERY_LOCK_START
; First, Read Device Identifier to obtain RCR value (a 2 cycle operation)
;
mov r0, #0x0
;ldr r2, =0x00980098 ; write "Read Query" (*NOTE: Consideration for cases where only a single FLASH: memc might break up into 2 commands for single flash!)
mov r2, #0x0098
mov r2, r2 LSL #16
orr r2, r2, #0x0098
str r2, [r0]
mov r0, #0x4 ; Read 2nd word: "Device Code" entry in Query Structure
ldr r8, [r0] ; 2nd cycle; r8 now contains the device code on upper and lower halves of data bus.
mov r0, #0x0
;ldr r1, =0x00FF00FF
mov r1, #0x00FF
mov r1, r1 LSL #16
orr r1, r1, #0x00FF
str r1, [r0] ; put back into read array mode
ALIGN 32 ; padding
QUERY_LOCK_END nop
;;;;ENDIF ;IF FLASH_WIDTH_16_BIT = "0" ;If we've got a 32-bit flash bus
ELSE
; So we've got a 16-bit device
ALIGN 32 ; ensure is cache-line aligned (i.e. 32 Bytes = 2^5)
QUERY_LOCK_START
; First, Read Device Identifier to obtain RCR value (a 2 cycle operation)
;
mov r0, #0x0
;ldr r2, =0x00980098 ; write "Read Query" (*NOTE: Consideration for cases where only a single FLASH: memc might break up into 2 commands for single flash!)
mov r2, #0x0098
str r2, [r0]
mov r0, #0x4 ; Read 2nd word: "Device Code" entry in Query Structure
ldr r8, [r0] ; 2nd cycle; r8 now contains the device code on upper and lower halves of data bus.
mov r0, #0x0
;ldr r1, =0x00FF00FF
mov r1, #0x00FF
str r1, [r0] ; put back into read array mode
;
str r4, [r3]
; If we had 2 devices, we'd jump up to the second, but we just assume
; the same device for now:
;
; TODO: Make this check for a second device and do the right thing
ALIGN 32 ; padding
QUERY_LOCK_END nop
ENDIF ;IF FLASH_WIDTH_16_BIT = "1" ;If we've got a 32-bit flash bus
; insert locking cleanup code here
;
ALIGN 32
mcr p15, 0, r0, c9, c1, 1 ; unlock entire i$
mov r0, #0x78
mcr p15, 0, r0, c1, c0, 0 ; disable i$ now that we are done with it
CPWAIT r0
mcr p15, 0, r0 ,c7, c5, 0 ; flush i$ and BTB
mov pc, lr ; Return
; ****************************************************************************
; ****************************************************************************
; ****************************************************************************
ALIGN
GO_SYNC_FLASH
; ****************************************************************************
;
; Enter Sync. mode for K18/3 Flash. Lock config code into i$.
; **R8 is assumed to still contain the boot flash id in lower 16-bits.
;
cmp r8, #J3_128Mb_DEVCODE ; are we booting from the Mainboard's J3 FLASH? IF so, we will not mess with K18/3.
beq NO_SYNC_FLASH
;Are we running L3 (Tyax)? Right now doesn't work for sync. mode so need to skip!!
ldr r0, =L3_128Mb_DEVCODE
cmp r8, r0
bge NO_SYNC_FLASH
IF :DEF: SYNC_FLASH
;
; Since is K18/3, we will configure it to run in Syncronous burst-of-8 mode (==cache-line)
;
; insert locking code here
add r3, pc, #SYNCLOCK_START-(.+8)
mvn r0, #31
and r1, r3, r0 ; ensure is 32-byte aligned
add r2, pc, #SYNCLOCK_END-(.+8)
and r2, r2, r0 ; ensure is 32-byte aligned
mrc p15, 0, r0, c1, c0, 0 ; read (0x78) cp15.1
orr r0, r0, #0x1000 ; enable ICache
mcr p15, 0, r0, c1, c0, 0 ; write it
CPWAIT r0
mcr p15, 0, r0, c9, c1, 1 ; unlock entire i$
mcr p15, 0, r0 ,c7, c5, 0 ; flush i$ and BTB
LOCKLOOP2
mcr p15, 0, r1, c7, c5, 1 ; CYA: invalidate i$ line (same as we are about to lock - CAN affect a locked line!)
mcr p15, 0, r1, c9, c1, 0 ; lock line into icache, based on r1
cmp r1, r2 ; are we done?
add r1, r1, #32 ; increment to next cache-line
bne LOCKLOOP2
; Adjust K18 FLASH.RCR for optimal timing (platform-specific to Mainstone)
;
ldr r3, =CLK_BASE_PHYSICAL
GET_CCSR_L r0, r3, r2 ; r0 gets the value in CCSR_L
add r2, pc, #L_0-(.+8) ; r2 = pc-relative address of L_0 (i.e. base of array)
add r2, r2, r0 ; r2 = pc-relative address of proper LC index, based on 'L'
ldrb r1, [r2] ; grab RCR value from array[r2]
mov r5, r1 LSL #2 ; shift for SXCFNG.SXCL0
mov r1, r1 LSL #13 ; shift LC into proper location, reflecting << 2, for FLASH.RCR value
ldr r3, =0x21FFF ; mask value, reflecting << 2.
ldr r0, =0x7708 ; base RCR value: 7708 represents 0x1dc2 << 2 (RM=0, LC=3, WP=1(d/c), DH=0, WD=1(d/c), BS=1, CE=1, BL=2)
and r0, r0, r3 ; mask out LC (RCR[14:11])
orr r0, r0, r1 ; insert new RCR value *Must preserve R0 for locked code!
; Adust SXCFNG to match adjusted LC *Assumes shifted value in R5*
; (use LC value from array, inserting into SXCFNG[4:2]. *NOTE: if LC value > 7 is required, must consider SXCFNG[15])
;
ldr r3, =SXCNFG_VAL
mvn r1, #0x1C
and r3, r3, r1 ; mask out SXLC0
orr r4, r3, r5 ; insert adjusted SXLC0
ldr r3, =MEMC_BASE_PHYSICAL ; prime r3 oustide of locked region for use by locked code
ALIGN 32 ; ensure is cache-line aligned (i.e. 32 Bytes = 2^5)
SYNCLOCK_START
;
; ** Assumes R0 contains adjusted RCR.LC, R4 contains adjusted SXCFNG, and R3 contains MEMC_BASE_PHYSICAL **
;
; Write the new RCR value
; 2 cycle write: 1)0060, 2)0003
;
mov r2, #0x0060
mov r2, r2 LSL #16
orr r2, r2, #0x0060 ; results in 0x00600060
str r2, [r0] ; R0 primed above, outside locked region
; Cycle 2
mov r2, #0x0003
mov r2, r2 LSL #16
orr r2, r2, #0x0003
str r2, [r0] ; update RCR; FLASH now in SyncMode
; Put FLASH back into read array mode (not needed if we don't write before next sync read, but will do it here for completeness).
;
mov r0, #0x0
mov r1, #0x00FF
mov r1, r1 LSL #16
orr r1, r1, #0x00FF ; (results in 0x00FF00FF)
str r1, [r0] ; put back into read array mode
;
; Program sxcnfg
;
str r4, [r3, #0x1C]
ALIGN 32 ; padding
SYNCLOCK_END nop
; insert locking cleanup code here
;
ALIGN
mcr p15, 0, r0, c9, c1, 1 ; unlock entire i$
mov r0, #0x78
mcr p15, 0, r0, c1, c0, 0 ; disable i$ now that we are done with it
CPWAIT r0
mcr p15, 0, r0 ,c7, c5, 0 ; flush i$ and BTB
ENDIF
; ****************************************************************************
ALIGN
NO_SYNC_FLASH
mov pc, lr
LTORG ; Insert a literal pool here
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Matrix used for optmial LC, based on L param of CCSR
;
ALIGN 16 ; Start array on 16B boundary for index scheme: Index = &L0 + 'L'
L_0 DCB 3 ; placeholder
L_1 DCB 3 ; placeholder
L_2 DCB 3 ; * close
L_3 DCB 5
L_4 DCB 3
L_5 DCB 5
L_6 DCB 5
L_7 DCB 6
L_8 DCB 3 ; * close
L_9 DCB 4
L_A DCB 4
L_B DCB 5
L_C DCB 5
L_D DCB 5 ; * close
L_E DCB 6
L_F DCB 6
L_10 DCB 3 ; * close
L_11 DCB 0 ; * DE-FEATURED
L_12 DCB 0 ; * DE-FEATURED
L_13 DCB 0 ; * DE-FEATURED
L_14 DCB 0 ; * DE-FEATURED
L_15 DCB 0 ; * DE-FEATURED
L_16 DCB 0 ; * DE-FEATURED
L_17 DCB 0 ; * DE-FEATURED
L_18 DCB 0 ; * DE-FEATURED
L_19 DCB 0 ; * DE-FEATURED
L_1A DCB 0 ; * DE-FEATURED
L_1B DCB 0 ; * DE-FEATURED
L_1C DCB 0 ; * DE-FEATURED
L_1D DCB 6
L_1E DCB 6
L_1F DCB 3
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
END
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