📄 fwbvd1.s
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; write back mdrefr
;
str r4, [r1, #MDREFR_OFFSET]
ldr r4, [r1, #MDREFR_OFFSET]
nop
nop
; *****************************************************************************
; Step 7
;
; Access memory *not yet enabled* for CBR refresh cycles (8)
; - CBR is generated for all banks
tst r10, #(xlli_RCSR_SMR:OR:xlli_RCSR_GPR) ;
bne %F12 ; skip if sleep (or GPIO) reset.
ldr r2, =SDRAM_BASE_PHYSICAL
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
; Fix for erratum #116. Need to make up for ineffective first mem access.
; *Bman: leaving in for Bulverde, as I expect this errata to also exist there.
;
str r2, [r2]
12 ; skipped due to sleep (or GPIO) reset
;
; ****************************************************************************
; Step 11: Final Step: Enable APD if desired. BMAN: ok for sync FLASH? (not configged yet, but will be shortly after)*
;
ldr r3, [r1, #MDREFR_OFFSET]
; enable auto-power down
;
orr r3, r3, #MDREFR_APD
; write back mdrefr
;
;str r3, [r1, #MDREFR_OFFSET] ; bman: try without just in case is causing me pain...
; ****************************************************************************
; For now, we will max out the buffer strengths for SDRAM signals + A & D
; Seems to cause problems on some boards, so commenting this out until we
; have a better feel for how to derive these values rather than hackery.
;
ldr r2, =FPGA_REGS_BASE_PHYSICAL
GET_SW7 r0, r2 ; DOT(0)= POR buffers, noDOT(1)= Maxed out SDRAM buffers
cmp r0, #0
beq NOBUFFERMUCKYMUCK
ldr r3, =0xF0F0FFFF
ldr r2, [r1, #BSCNTR0_OFFSET] ; load current contents
orr r2, r2, r3 ; flip the bits we care about
str r2, [r1, #BSCNTR0_OFFSET] ; update reg
ldr r3, =0xFF0FF00F
ldr r2, [r1, #BSCNTR1_OFFSET] ; load current contents
orr r2, r2, r3 ; flip the bits we care about
str r2, [r1, #BSCNTR1_OFFSET] ; update reg
ldr r3, =0x0000000F
ldr r2, [r1, #BSCNTR2_OFFSET] ; load current contents
orr r2, r2, r3 ; flip the bits we care about
str r2, [r1, #BSCNTR2_OFFSET] ; update reg
ldr r3, =0xFFFFFFFF
ldr r2, [r1, #BSCNTR3_OFFSET] ; load current contents
orr r2, r2, r3 ; flip the bits we care about
str r2, [r1, #BSCNTR3_OFFSET] ; update reg
ALIGN
NOBUFFERMUCKYMUCK
IF BSP_MAINSTONE = "1"
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0x000c0de1
setHexLED r1, r0
ENDIF
mov pc, lr
;;
;; End of INITMEMC
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
LTORG ; Insert a literal pool here
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
INITCLKS
ldr r1, =CLK_BASE_PHYSICAL
; Turn only clocks that are necessary (MEMC, OST, BTUART), hzh use BTUART
;
ldr r2, =CKEN_DEFAULT
str r2, [r1, #CKEN_OFFSET]
IF :DEF: USE32KOSC
; enable the 32Khz oscillator for RTC and PowerManager
;
mov r2, #OSCC_OON
str r2, [r1, #OSCC_OFFSET]
; **NOTE: Spin here until OSCC.OOK gets set,
; meaning the 32KHz PLL has settled.
;
60
ldr r2, [r1, #OSCC_OFFSET]
ands r2, r2, #1
beq %B60
ENDIF
OSCC_OON_DONE
IF BSP_MAINSTONE = "1"
; enable 32KHz OSC output on GPIO[10] (CLK_TOUT) and
; enable 13MHz output on GPIO[9] (CLK_PIO)...
;
ldr r2, [r1, #OSCC_OFFSET]
orr r2, r2, #(OSCC_TOUT_EN) ;#(OSCC_TOUT_EN :OR: OSCC_PIO_EN)
str r2, [r1, #OSCC_OFFSET]
ENDIF
IF BSP_MAINSTONE = "1"
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0x000c0de3
setHexLED r1, r0
ENDIF
mov pc, lr
LTORG ; Insert a literal pool here
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
INITPLATFORM
[ {FALSE} ;hzh
IF BSP_MAINSTONE = "1"
; ********************************************************************
; Do Mainstone-Specific Board Initialization
;
ldr r2, =FPGA_REGS_BASE_PHYSICAL
; setup MISC_WR1,2 to their initial states
;
ldr r1, =MISCWR1_VAL
str r1, [r2, #MISCWR1_OFFSET]
ldr r1, =MISCWR2_VAL
str r1, [r2, #MISCWR2_OFFSET]
; mask all of the platform-level interrupts
;
mov r1, #INTMSKEN1_VAL
str r1, [r2, #INTMSKEN1_OFFSET]
; clear any platform-level interrupts
;
mov r1, #INTSETCLR1_VAL
str r1, [r2, #INTSETCLR_OFFSET]
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0007
setHexLED r1, r0
ENDIF
]
mov pc, lr
LTORG ; Insert a literal pool here
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
SCRUB_SDRAM
; ****************************************************************************
; Scrub SDRAM iff Hard-Reset.
;
; 64MB: Bulverde
;
tst r10, #RCSR_GPIO_RESET ; skip RAM scrub after GPIO reset
bne showGot_SOFT_RESET ; but announce we got a soft reset
tst r10, #xlli_RCSR_SMR ; Skip scrub after sleep,
bne END_DISPLAY ; need RAM contents
add r2, pc, #START_SCRUBBING-(.+8)
ldr r1, =FFUART_BASE_PHYSICAL ; Tx start
PrintStr r1, r2, r3
SCRUB_SDRAM_TUNED_64 r1, r2, r3, r4, r5, r6 ; hardcoded for 64MB scrub
add r2, pc, #END_SCRUBBING-(.+8)
ldr r1, =FFUART_BASE_PHYSICAL ; Tx end
PrintStr r1, r2, r3
b END_DISPLAY
showGot_SOFT_RESET
ldr r1, =FFUART_BASE_PHYSICAL
ldr r2, =(SOFT_RST_STR-(.+8))
add r2, pc, r2 ;
PrintStr r1, r2, r3
b END_DISPLAY
END_DISPLAY
mov pc, lr
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;; Data used for FFUART Transmissions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Misc. Strings
;
ALIGN
SOFT_RST_STR DCB 0xA, 0xD, " Got Soft Reset", 0xA, 0xD, 0
ALIGN
MainLabel DCB 0xA, 0xD, 0xA, 0xD, "main.....", 0xA, 0xD, 0
ALIGN
START_SCRUBBING DCB 0xA, 0xD, "Beginning SDRAM Scrub...liudiping", 0xA, 0xD, 0
ALIGN
END_SCRUBBING DCB "SDRAM Scrub Complete", 0xA, 0xD, 0
CR_LF DCB 0xA, 0xD, 0
ALIGN
VERIFY_FAILURE_MSG DCB 0xA, 0xD, 0xA, 0xD, "**FLASH to SDRAM verification failed at SDRAM address on HEX LEDs. Halting.**", 0xA, 0xD, 0
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
INITMMU
; *****************************************************************
; Load RVA of OEMAddressTable[]
;
add r0, pc, #OEMAddressTable-(.+8) ; (r0) = OEMAddressTable phys addr *DO NOT DESTROY THIS VALUE
mov r11, r0 ; (r11) = &MemoryMap (save pointer for later)
IF BSP_MAINSTONE = "1"
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r2, =0x000c0de8
setHexLED r1, r2
ENDIF
IF :LNOT: :DEF: ETHBOOT
bl KernelStart ; Branch to coreos\armtrap.s::KernelStart()
; should not return, NK now in control
nop
nop
nop
DEADLOOP
b DEADLOOP
ENDIF
; For GPIO / soft reset, don't go to Eboot main(), go to launch address from load.
;dd r2, pc, #START_SCRUBBING-(.+8)
;dr r1, =FFUART_BASE_PHYSICAL ; Tx start
;rintStr r1, r2, r3
tst r10, #RCSR_GPIO_RESET
beq CONTINUE
; Get previously saved launch address
ldr r4, =(RESET_LAUNCH_ADDR_PHYSICAL) ; pointer
ldr r3, [r4] ; launch address
ldr r2, =PhysicalStart
;
; First, we need to find the Offset that will get us from Virtual->Physical for
; the EBOOT Partition
;
ldr r5, =(EBOOT_PARTITION_PHY_BASE - SDRAM_VIR_C_EBOOT_PARTITION)
;
; Next, we add the above found Offset to PhysicalStart's RVA.
; (R2 now points to the Physical address of PhysicalStart (below).)
;
add r2, r2, r5
mov r1, r10 ; Contains soft reset indicators.
ldr r0, =(FPGA_REGS_BASE_PHYSICAL+LEDDAT1_OFFSET)
IF Interworking :LOR: Thumbing
bx r2
ELSE
mov pc, r2
ENDIF
nop ; These NOPs are used to flush the Pipeline
nop
nop
nop
nop
nop
nop
nop
b CONTINUE ; branch around Include (do not move)
INCLUDE MemMap.inc ; **NOTE: DO NOT move this! Must be in this section
CONTINUE
; *****************************************************************
; Copy Flash-based Eboot image into RAM. This will be placed
; in our EBOOT_PARTITION plus an offset. (EbootOffset)
;
;
; The bootloader is linked to run from RAM but is initially installed in "FLASH" Ram
; at the reset/boot address. Now that memory has been configured, copy the
; entire bootloader image to RAM.
;
; *Note: The bootloader's region size must agree with boot.bib's declaration of
; it.
;
ldr r8, =BOOT_FLASH_BASE_PHYSICAL ; Phy Base of our EBOOT PARTITION
ldr r1, =(EBOOT_PARTITION_PHY_BASE + EbootOffset) ; **Defined in BOOT.BIB. Is the offset into the EBOOT PARTITION.
; This (and next) values must match BOOT.BIB!
ldr r2, =(EBootImageLen/16) ; Setup Loop control. We are block-copying 16-bytes per iteration.
; **EBootImageLen From BOOT.BIB, size field.
;
; Do 4x32-bit Block Copies from Flash->SDRAM (corrupts r4-r7)
;
10 ldmia r8!, {r4-r7} ; Loads from BOOT_FLASH_BASE_PHYSICAL, post increment
stmia r1!, {r4-r7} ; Stores to (EBOOT_PARTITION_PHY_BASE+EbootOffset), post increment
subs r2, r2, #1
bne %B10
;;;;;;;;;;; BMAN: check the contents of RAM while we are still in flash ;;;;;;;;;;;;;;;;;;
ldr r0, =EBootImageLen ; 0x2000
ldr r1, =(EBOOT_PARTITION_PHY_BASE + EbootOffset) ; SDRAM start Adx
ldr r2, =BOOT_FLASH_BASE_PHYSICAL ; FLASH start Adx
VERIFY
ldr r3, [r1], #4 ; read word from SDRAM
ldr r4, [r2], #4 ; read word from FLASH
cmp r3, r4 ; and compare them
bne VERIFY_FAILURE ; if not the same, quit!
subs r0, r0, #4
bne VERIFY
b VDONE
VERIFY_FAILURE
ldr r0, =FPGA_REGS_BASE_PHYSICAL
sub r1, r1, #4 ; get back to real failure
setHexLED r0, r1 ; display failing adx
add r2, pc, #VERIFY_FAILURE_MSG-(.+8)
ldr r1, =FFUART_BASE_PHYSICAL ; Tx end
PrintStr r1, r2, r3
STALL
b STALL
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