📄 fwbvd1.s
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mcr p15, 0, r0, c3, c0, 0
; Soft Resets: Info carried in R10. If soft reset, this could be the second
; time through (if loaded from Eboot). In that case, r10 will be nonzero,
; so use that to skip redundant operations that would also corrupt r10.
;liudiping
;power manage
;ands r10, r10, r10 ;tow lines masked by hzh
;beq got_SOFT_RESET_PREINIT
; ********************************************************************
; Read & Init Reset Cause bits in RCSR.
;
ldr r0, =PWR_BASE_PHYSICAL
ldr r10, [r0, #RCSR_OFFSET]
; extract the reset cause bits
;
mov r2, #RCSR_ALL ; Mask RCSR
and r10, r10, r2 ; r10 now holds the conditioned Reset Reason
; clear the reset cause bits (they're sticky)
;
str r2, [r0, #RCSR_OFFSET]
; ********************************************************************
; Read and store PSSR, too - it will be reset later, after GPIOs are initialized.
; Unclear when we'll need this information, but don't throw a good status away.
; **BMAN: We really should stick this into driver_globs so that we are not so limited on our register usage!!
ldr r0, =PWR_BASE_PHYSICAL
ldr r12, [r0, #PSSR_OFFSET]
; Set VIDAE and BIDAE for VDD/Batt Fault --> IDA
;
mov r1, #(PMCR_BIDAE:OR:PMCR_VIDAE) ; configure for imprecise dAbort on VDD and BATT Faults. *Can set up as an intrerrupt if desired*
str r1, [r0, #PMCR_OFFSET]
; extract the reset cause bits
;
mov r2, #PSSR_VALID_MASK ; Mask PSSR (All in lower byte)
and r12, r12, r2 ; r12 now holds the conditioned PSSR
mov r12, r12, lsl #16 ; Move to upper half of register
orr r10, r10, r12 ; R10 now has RCSR in lower half and PSSR in upper.
got_SOFT_RESET_PREINIT
mov pc, lr
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
INITGPIO
; ********************************************************************
; Set Alternate Functions, etc. *Note: LEDs (HEX & discrete) are
; inactive until this routine completes.
;
ldr r1, =GPIO_BASE_PHYSICAL
; First, Set GPSRx,y,z HIGH for active low outputs...
;
ldr r2, =GPSR0_VAL
str r2, [r1, #GPSR0_OFFSET]
ldr r2, =GPSR1_VAL
str r2, [r1, #GPSR1_OFFSET]
ldr r2, =GPSR2_VAL
str r2, [r1, #GPSR2_OFFSET]
ldr r2, =GPSR3_VAL
str r2, [r1, #GPSR3_OFFSET]
; ...then Set GPCR LOW for active high outputs
;
ldr r2, =GPCR0_VAL
str r2, [r1, #GPCR0_OFFSET]
ldr r2, =GPCR1_VAL
str r2, [r1, #GPCR1_OFFSET]
ldr r2, =GPCR2_VAL
str r2, [r1, #GPCR2_OFFSET]
ldr r2, =GPCR3_VAL
str r2, [r1, #GPCR3_OFFSET]
; Next, Set GPDR accordingly for all pins
;
ldr r2, =GPDR0_VAL
str r2, [r1, #GPDR0_OFFSET]
ldr r2, =GPDR1_VAL
str r2, [r1, #GPDR1_OFFSET]
ldr r2, =GPDR2_VAL
str r2, [r1, #GPDR2_OFFSET]
ldr r2, =GPDR3_VAL
str r2, [r1, #GPDR3_OFFSET]
; Finally, set GAFR0,1,2,3 for alternate functions
;
ldr r2, =GAFR0_L_VAL
str r2, [r1, #GAFR0_L_OFFSET]
ldr r2, =GAFR0_U_VAL
str r2, [r1, #GAFR0_U_OFFSET]
ldr r2, =GAFR1_L_VAL
str r2, [r1, #GAFR1_L_OFFSET]
ldr r2, =GAFR1_U_VAL
str r2, [r1, #GAFR1_U_OFFSET]
ldr r2, =GAFR2_L_VAL
str r2, [r1, #GAFR2_L_OFFSET]
ldr r2, =GAFR2_U_VAL
str r2, [r1, #GAFR2_U_OFFSET]
ldr r2, =GAFR3_L_VAL
str r2, [r1, #GAFR3_L_OFFSET]
ldr r2, =GAFR3_U_VAL
str r2, [r1, #GAFR3_U_OFFSET]
; Next, clear the RDH and PH bits in the PSSR
; to allow GPIO's configged as inputs to function
; *NOTE: There is status here that we may want for wakeup. It's in r12, but i dont plan to reserve this reg. Must put into driver_globs asap (i.e. after initmemc)
;
ldr r0, =PWR_BASE_PHYSICAL
mov r1, #0x30 ; set-to-clear RDH and PH
str r1, [r0, #PSSR_OFFSET]
IF BSP_MAINSTONE = "1"
ldr r3, =MEMC_BASE_PHYSICAL
ldr r2, =MSC1_VAL
str r2, [r3, #MSC1_OFFSET] ; need to set MSC1 before trying to write to the HEX LEDs
ldr r2, [r3, #MSC1_OFFSET] ; need to read it back to make sure the value latches (see MSC section of manual)
ldr r1, =FPGA_REGS_BASE_PHYSICAL
mov r0, #0x0
str r0, [r1, #LEDCTL_OFFSET] ; blank hex & discrete leds
ldr r0, =0x000c0de0
setHexLED r1, r0
ENDIF ; BSP_MAINSTONE
mov pc, lr
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
INITMEMC
bl QUERY_FLASH_CFI ; grab the Flash ID - return is in R8!!!!!
; get memory controller base address
ldr r1, =MEMC_BASE_PHYSICAL
; ****************************************************************************
; Step 1
;
;
; Initialize Static Memory Timings
;
; write msc0, read back to ensure data latches
;
ldr r0, =0xFFFF
and r8, r8, r0 ; mask lower 16 only; *assumes r8 still contains device code
ldr r0, =L3_128Mb_DEVCODE ; Right now Tyax can't do sync. mode
cmp r8, r0
ldrge r2, =L3_MSC0_VAL
ldrlt r2, =K3_MSC0_VAL ; *NOTE: I touch this again in Step 3 to automatically set MSC0
str r2, [r1, #MSC0_OFFSET]
;-------------------------------------------------------
; 4th bullet, Step 1 : if coming out of Sleep, must explicitly
; CLEAR all SDRAM partitions via MDCNFG[17:16, 1:0]. *
;
; IF :DEF: TESTSLEEP
; need to check RCSR status here... inserting config code, will need cmp later
tst r10, #xlli_RCSR_SMR ;
beq memNotSleepReset
ldr r2, [r1, #MDCNFG_OFFSET]
bic r2, r2, #(MDCNFG_DE0 :OR: MDCNFG_DE1)
bic r2, r2, #(MDCNFG_DE2 :OR: MDCNFG_DE3)
str r2, [r1, #MDCNFG_OFFSET]
; ENDIF
memNotSleepReset
; ****************************************************************************
; Step 2: Not configuring SXCFNG here; doing it after INITCLKS
;
; ****************************************************************************
; Step 3
;
; Assumes previous mdrefr value in r4, if not then read current mdrefr.
; Assumes boot FLASH ID still in R8.
; 1st Bullet: set K1RUN if bank 0 installed
;
orr r4, r4, #MDREFR_K1RUN
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Ensure SDCLK is halved when it absolutely needs to be. ;
;
; Methodology: A HEX pair for each element in Table 3-7.
;
; Sw5,9 (HEX) L (DEC) MEMCLK NOTES
; -----------------------------------------------------------
; 0-4 2 26
; 5-9 3 39
; A-E 4 52
; F-13 5 65
; 14-18 6 78 A
; 19-1d 7 91 A
; 1e-22 8 104 A
; 23-27 9 117 *
; 28-2c 10 130 *,C
; 2d-30 11 71.5 A
; 31-34 12 78 A
; 35-37 13 84.5 A
; 38-3a 14 91 A
; 3b-3d 15 97.5 A
; 3e-3f 16 104 A
; 40 29 94.25 A
; 41 30 97.5 A
; 42 31 100.75 A
;
; LEGEND:
; * - Must Force SDCLK = MEMCLK/2 due to resultant SDCLK[1] > 104 MHz.
; A - Bulverde A0 cannot run SDCLK > 66MHz on 1.8V VCC_MEM systems. Will _not_ force SDCLK = MEMCLK/2, but is considered out of spec otherwise.
; B - 'B' bit cannot be set with this frequency combination. I will force B=0 for these combos.
; C - Must re-program MSC[x] value(s) for the resultant MEMCLK.
;
; Set MDREFR.K1DB2 to halve the MemClk for desired SDCLK[1]
;
; Switch for k1db2: using sw4: DOT(0): K1db2=1 (SDCLK[1] = MemClk/2)
; !DOT(1): 1db2=0 (SDCLK[1] = MEmClk)
;
ldr r2, =FPGA_REGS_BASE_PHYSICAL
GET_SW4 r3, r2 ; get the value in r3
cmp r3, #0x0 ; is DOT?
orreq r4, r4, #0x00020000 ; SDClk[1] = MemClk/2
bicne r4, r4, #0x00020000 ; SDClk[1] = MemClk
GET_HEXSW5 r0, r2
GET_HEXSW9 r3, r2
orr r3, r3, r0
IF :DEF: SYNC_FLASH
cmp r8, #J3_128Mb_DEVCODE ; are we booting from the mainboard's J3 FLASH?
beq SYNCDONE ; booting from J3; skip K18 code below
;Are we running L3 (Tyax)? Right now doesn't work for sync. mode so need to skip!!
ldr r0, =L3_128Mb_DEVCODE
cmp r8, r0
bge SYNCDONE
;
; If Boot FLASH device is DaughterCard's K18, we can go syncronous with it (based on SYNC_FLASH)
; Therefore, need to provide optimal timing paramters for SDCLK[0]. Also need to ensure RCR.LC is optimal (done at the end of INITCLKS).
;
cmp r3, #0x09
bicle r4, r4, #MDREFR_K0DB4 ; MemClk < 52 MHz; no need to halve or quarter Sdclk
bicle r4, r4, #MDREFR_K0DB2 ; CYA
ble SYNCDONE
; must be greater than '09'...
;
cmp r3, #0x1D
bicle r4, r4, #MDREFR_K0DB4
orrle r4, r4, #MDREFR_K0DB2
ble SYNCDONE
; must be greater that '1d' ...
;
cmp r3, #0x2D
blt SYNCDONE ; If L=9 or 10, no adjustments needed (k0db4 already set in previous step)
; must be greater or equal to '2d'
;
cmp r3, #0x3D
bicle r4, r4, #MDREFR_K0DB4
orrle r4, r4, #MDREFR_K0DB2
ble SYNCDONE
; must be greater than '3d'
;
cmp r3, #0x40
biceq r4, r4, #MDREFR_K0DB4
orreq r4, r4, #MDREFR_K0DB2
cmp r3, #0x41
biceq r4, r4, #MDREFR_K0DB4
orreq r4, r4, #MDREFR_K0DB2
ENDIF
ALIGN
SYNCDONE
;
; Need to force sdclk to be halved and alter MSCs for some freqs
;
cmp r3, #0x2C
bgt NOADJUSTMENT ; targetting L(9->10) for SDCLK and MSC0 fixups due to MEMClk
cmp r3, #0x23
blt NOADJUSTMENT
;
; Now, must re-program MSC0 for FLASHes where MEMCLKs force an adjustment
; Currently, only seeing problems with MEMCLK=117 and 130MHZ (i.e. L=9 & 10).
;
; *NOTE: R8 needs to contain the results from the flash detect in the early steps
;
cmp r8, #J3_128Mb_DEVCODE ; are we booting from the mainboard's J3 FLASH?
ldr r2, [r1, #MSC0_OFFSET] ; get current MSC0 value... will be adjusting it
;
; ~~ ADJUST MSC0 for Higher MemClks ~~
;
; **NOTE: It is invalid to run J3 on mainboard at MemClk = 130MHz **
; Therfore, targetting MemClk = 117 MHz, which is possible to acheive.
; J3 Boot device adjustments
;
biceq r2, r2, #0x7F00 ; clear RRR0 and RDN0 for J3
orreq r2, r2, #0x5A00 ; set RRR0 = 5, and RDN0 = 10 (0xA) for J3
biceq r2, r2, #0xF00000 ; clear current RDF1 for K3/18
orreq r2, r2, #0xE00000 ; set RDF1 = 14 (0xE) for K3/18
beq J3_ADJUSTMENT_DONE
;Are we running L3 (Tyax)? Right now doesn't work for sync. mode so need to skip!!
ldr r0, =L3_128Mb_DEVCODE
cmp r8, r0
bicge r2, r2, #0x7F00 ; clear RRR0 and RDN0 for J3
orrge r2, r2, #0x5A00 ; set RRR0 = 5, and RDN0 = 10 (0xA) for J3
bicge r2, r2, #0xF00000 ; clear current RDF1 for K3/18
orrge r2, r2, #0xE00000 ; set RDF1 = 14 (0xE) for K3/18
bge J3_ADJUSTMENT_DONE ; Right now, skip, use J3's ASYNC. values !EJV - NEED TO FIX when Tyax is
; K3/K18 Boot device adjustments
;
biclt r2, r2, #0xF0 ; clear current RDF0 for K3/18
orrlt r2, r2, #0xE0 ; set MSC0[RDF0] = 14 (0xE) for K3/18
biclt r2, r2, #0x7F000000 ; clear RRR1 and RDN1 for J3
orrlt r2, r2, #0x5A000000 ; set RRR1 = 5 and RDN1 = 10 (A)
J3_ADJUSTMENT_DONE
str r2, [r1, #MSC0_OFFSET] ; store it back
ldr r2, [r1, #MSC0_OFFSET] ; ensure it latches
;
; Enforce/override halving where needed, regardless of CPU stepping
; (the user needs to be careful with A0's VCC_MEM: see release notes and EMT)
;
orr r4, r4, #0x00020000 ; SDClk[1] = MemClk/2 regardless of what user wants
; ;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ALIGN
NOADJUSTMENT
; write back mdrefr
;
str r4, [r1, #MDREFR_OFFSET]
ldr r4, [r1, #MDREFR_OFFSET]
; 2nd Bullet: deassert SLFRSH
;
bic r4, r4, #MDREFR_SLFRSH
; write back mdrefr
;
str r4, [r1, #MDREFR_OFFSET]
ldr r4, [r1, #MDREFR_OFFSET]
; 3rd Bullet: assert E1PIN
;
orr r4, r4, #MDREFR_E1PIN
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