📄 fwbvd1.s
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;----------------------------------------------------------------------------------------
;
; INTEL CONFIDENTIAL
; Copyright 2000-2003 Intel Corporation All Rights Reserved.
;
; The source code contained or described herein and all documents
; related to the source code (Material) are owned by Intel Corporation
; or its suppliers or licensors. Title to the Material remains with
; Intel Corporation or its suppliers and licensors. The Material contains
; trade secrets and proprietary and confidential information of Intel
; or its suppliers and licensors. The Material is protected by worldwide
; copyright and trade secret laws and treaty provisions. No part of the
; Material may be used, copied, reproduced, modified, published, uploaded,
; posted, transmitted, distributed, or disclosed in any way without Intel抯
; prior express written permission.
; No license under any patent, copyright, trade secret or other intellectual
; property right is granted to or conferred upon you by disclosure or
; delivery of the Materials, either expressly, by implication, inducement,
; estoppel or otherwise. Any license under such intellectual property rights
; must be express and approved by Intel in writing.
;
;
; Module Name:
;
; fwBvd1.s
;
; Abstract:
;
; This module implements the code necessary to initialize the HW and
; Kernel interface routines.
;
;
; Register Useage: r10 is used to hold the contents of the RCSR throughout this module.
; The rest of the registers are fair game.
;
;
;----------------------------------------------------------------------------------------
OPT 2 ; disable listing
INCLUDE kxarm.h
INCLUDE Bvd1.inc
INCLUDE Bvd1bd.inc
INCLUDE xlli_Bulverde_defs.inc
INCLUDE xllp_Pm_SleepContext.inc ; Needed for sleep reset processing
;
; Conditional Includes
;
IF BSP_MAINSTONE = "1"
INCLUDE Mainstone.mac
ENDIF
OPT 1 ; reenable listing
;OPT 128 ; disable listing of macro expansions
IMPORT xlli_GPIO_init
IMPORT xlli_mem_init
IMPORT xlli_intr_init
IMPORT xlli_clks_init
IMPORT xlli_ost_init
IMPORT xlli_pwrmgr_init
IMPORT xlli_IMpwr_init
IMPORT xlli_mem_Tmax
IMPORT xlli_setClocks
IMPORT xlli_freq_change
IMPORT xlli_mem_Topt
IMPORT xlli_mem_restart
IMPORT XllpPmValidateResumeFromSleep
IMPORT XllpPmGoToContextRestoration
IMPORT DISPLAY_FREQS ; for displaying the set frequencies out the FFUART
IMPORT QUERY_FLASH_CFI ; for grabbing the flash ID from the flash CFI area
IMPORT GO_SYNC_FLASH ; For enabling sync. flash mode - not flushed out yet - DO NOT USE YET!!!!
EXPORT SCRUB_SDRAM
EXPORT INITGPIO
EXPORT INITPLATFORM
EXPORT INITMMU
EBOOT_PARTITION_PHY_BASE EQU SDRAM_PHY_EBOOT_PARTITION
EBOOT_PARTITION_VIR_C_BASE EQU SDRAM_VIR_C_EBOOT_PARTITION
IF :LNOT: :DEF: ETHBOOT ; see eboot\fwp2.s
IMPORT KernelStart ; If using module as CE Bringup (i.e. Eboot handoff)
ELSE
IMPORT main ; If using module as POR init code
ENDIF
STARTUPTEXT
;************************************************************************
; StartUp() is the entry point on Reset (all forms of Reset)
;
; Desription: StartUp is the first routine executed when powering on
; the system. It is also executed first after all forms of XScale
; resets.
;
; This code is shared between EBOOT and the CE Kernel. The flag 'ETHBOOT' denotes
; if the code is built for EBOOT or CE Kernel initialization (.nb0).
;
; Regardless of the build type, we disable the MMU and caches
; immediately and flush'em.
;
; This routine includes all of the necessary board and core-level
; initialization code to get Mainstone up.
;
;
;************************************************************************
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Note 1: Normally, we'd have our exception vectors here, but the MS tools
; currently insert a 4K "jump page" at the start of the image.
; Therefore, we do NOT have control of the vector code. They insert a branch
; to StartUp at physical address 0.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Note 2: - MMU assumed to be inactive at this time, so use physical addresses
;;
LEAF_ENTRY StartUp
mov r10, r1 ; During Soft Reset with bootloader in place, r1 contains indicators.
bl PREINIT ; always call, regardless if using xlli
IF :LNOT: :DEF: ETHBOOT
IF _FLASH != "1"
b INITMMU
ENDIF
ENDIF
bl INITGPIO
;bl xlli_GPIO_init
ldr r1, =FPGA_REGS_BASE_PHYSICAL
mov r0, #0x0
str r0, [r1, #LEDCTL_OFFSET] ; blank hex & discrete leds
ldr r0, =0xc0de0000
setHexLED r1, r0
;; Need to check for GPIO reset early, before memcontrollers are hit.
tst r10, #RCSR_GPIO_RESET
bne GOT_GPIO_RESET
;bl INITMEMC
bl xlli_mem_init
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0x000c0de1
setHexLED r1, r0
; After some basic init, try to resume if sleep reset.
ldr r0, =xlli_PMRCREGS_PHYSICAL_BASE ; Get the Power Manager base address
ldr r0, [r0, #xlli_PSPR_offset] ; And the contents of the PSPR
mov r1, r10 ; Packed RCSR+PSSR
bl XllpPmValidateResumeFromSleep ; R0 .. R6 lost
cmp r0, #0 ; Zero return: OK to restore
bne ResetFailedRestore ; Maybe not even a sleep reset.
;; NOTE: GPIO reset and sleep-mediated soft reset require the
;; same handling. So sleep-based soft reset will return,
;; but #RCSR_GPIO_RESET will be forced in r10 just below.
ldr r3, =(SLEEP_TYPE_PHYSICAL)
ldr r1, [r3]
cmp r1, #SLEEP_TYPE_SOFT_RESET
bne Sleep_Reset_Not_SoftReset
; For soft reset, force same execution path as GPIO reset
; Also invalidate checksum and change sleep type at the same time.
mov r1, #SLEEP_TYPE_STANDARD
str r1, [r3]
ldr r3, =(SLEEP_SAVE_PHYSICAL_BASE) ; checksum always at sleep base addr
ldr r1, [r3] ; Get checksum
add r1, r1, #1 ; Change
str r1, [r3] ; Put bad checksum
; for now, make Sleep-based Soft Rest look like GPIO reset.
orr r10, r10, #RCSR_GPIO_RESET
b GOT_GPIO_RESET
Sleep_Reset_Not_SoftReset
ldr r0, =xlli_PMRCREGS_PHYSICAL_BASE ; Get the Power Manager base address
ldr r0, [r0, #xlli_PSPR_offset] ; Phys. addr of save data
mov r1, r10 ; Packed RCSR+PSSR
b XllpPmGoToContextRestoration ; Never returns.
ResetFailedRestore
; A failed resumability check is treated as no sleep
ldr r1, =xlli_RCSR_SMR
bic r10, r10, r1
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0001
setHexLED r1, r0
;bl INITINTC
bl xlli_intr_init
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0002
setHexLED r1, r0
; Neet to init clocks here -
bl INITCLKS ; We will still use ours for now - XLLI touches the RTC for the moment
; and also does NOT enable the FFUART!
;Initialize the clocks with the following XLLI sequence
bl xlli_mem_Tmax
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0012
setHexLED r1, r0
bl xlli_mem_restart
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0022
setHexLED r1, r0
bl xlli_setClocks ; will poke CCCR so must do Frequency Change
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0032
setHexLED r1, r0
bl xlli_freq_change
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0042
setHexLED r1, r0
bl xlli_mem_Topt
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de00052
setHexLED r1, r0
bl xlli_mem_restart
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0003
setHexLED r1, r0
;bl INITOST
bl xlli_ost_init
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0004
setHexLED r1, r0
bl xlli_pwrmgr_init
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0005
setHexLED r1, r0
bl xlli_IMpwr_init
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0006
setHexLED r1, r0
bl INITPLATFORM
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0016
setHexLED r1, r0
;liudiping
;ldr r1, =GPIO_BASE_PHYSICAL
;ldr r0, =0x00001800
;str r0,[r1,#GPSR3_OFFSET]
bl DISPLAY_FREQS ;display freq through BTUART, modified by hzh(InitFFUART also in this func.)
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0017
setHexLED r1, r0
bl SCRUB_SDRAM
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0018
setHexLED r1, r0
b INITMMU
GOT_GPIO_RESET
; Currently GPIO reset is implemented as "Soft Reset" - that is, entered through the sleep process
; and flag status checked
; TODO: EV: We can simply create an interrupt that simulates GPIO reset by resetting the registers
; to boot-up conditions, resetting the peripheral registers so the drivers have a clean slate and
; and branching back to KernelStart as opposed to having to enter via sleep.
; GPIO reset could be enabled, but given that the HW doesn't put SDRAM into self-refresh, what's the point...
;
bl xlli_intr_init ; use for soft reset
; CCCR and OSCC are maintained through GPIO reset. But init after Sleep Soft Reset
bl INITCLKS ; We will still use ours for now - XLLI touches the RTC for the moment
; and also does NOT enable the FFUART!
;Initialize the clocks with the following XLLI sequence
bl xlli_mem_Tmax
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0060
setHexLED r1, r0
bl xlli_mem_restart
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0061
setHexLED r1, r0
bl xlli_setClocks ; will poke CCCR so must do Frequency Change
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0062
setHexLED r1, r0
bl xlli_freq_change
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0063
setHexLED r1, r0
bl xlli_mem_Topt
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0064
setHexLED r1, r0
bl xlli_mem_restart
ldr r1, =FPGA_REGS_BASE_PHYSICAL
ldr r0, =0xc0de0065
setHexLED r1, r0
bl xlli_ost_init ; use for soft reset
; bl xlli_pwrmgr_init ; PCFR, among others. PCFR is not affected by GPIO reset or sleep in an interesting way.
bl xlli_IMpwr_init
; May not need for Mainstone II - FPGA and Ethernet controller are maintained. But init after Sleep Soft Reset
bl INITPLATFORM
;liudiping
ldr r1, =GPIO_BASE_PHYSICAL
ldr r0, =0x00001000
str r0,[r1,#GPSR3_OFFSET]
bl DISPLAY_FREQS
b INITMMU
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;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
PREINIT
; ********************************************************************
; Set processor into Supervisior mode (SVC) and disable IRQ & FIQ
;
ldr r0, =(Mode_SVC :OR: NoIntsMask)
msr cpsr_c, r0
; ********************************************************************
; Grab the CPU ID off of CP15, stuff it into Driver Globals
;
mrc p15, 0, r9, c0, c0, 0 ; Grab CPU ID
and r9, r9, #0xF ; Grab only the lowest nibble as it's all we care about
; ********************************************************************
; Disable the MMU and gang regardless of why we are here.
;
ldr r0, =0x2043 ; enable access to all coprocessors
mcr p15, 0, r0, c15, c1, 0
CPWAIT r0
ldr r0, =0x00000078 ; get a zero to turn things off (must write bits[6:3] as 1's)
mcr p15,0,r0,c1,c0,0 ; Turn Off MMU, I&D Caches, WB.
CPWAIT r0
ldr r0, =0x00000000 ; get a zero to turn things off
mcr p15, 0, r0, c8, c7, 0 ; flush (invalidate) I/D tlb's
mcr p15, 0, r0, c7, c7, 0 ; flush (invalidate) I/D caches
mcr p15, 0, r0, c7, c10, 4 ; Drain the write buffer
nop
nop
nop
mvn r0, #0 ; grant manager access to all domains
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