pmgr.c

Xcale270Bsp包,wince平台

/******************************************************************************
**
** INTEL CONFIDENTIAL
** Copyright 2000-2003 Intel Corporation All Rights Reserved.
**
** The source code contained or described herein and all documents
** related to the source code (Material) are owned by Intel Corporation
** or its suppliers or licensors.  Title to the Material remains with
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** Material may be used, copied, reproduced, modified, published, uploaded,
** posted, transmitted, distributed, or disclosed in any way without Intel抯
** prior express written permission.
**
** No license under any patent, copyright, trade secret or other intellectual
** property right is granted to or conferred upon you by disclosure or
** delivery of the Materials, either expressly, by implication, inducement,
** estoppel or otherwise. Any license under such intellectual property rights
** must be express and approved by Intel in writing.
**
**  FILENAME:   pmgr.c
**
**  PURPOSE:    contains C-level power manager code
**
******************************************************************************/
#define __PMGR_C_
#include "xllp_defs.h"
#include "xllp_pm.h"
#include "xllp_clkmgr.h"
#include "xllp_Pm_ProcRegInfo.h"        // Defines register offsets from base address for specific processor
#include "xllp_Pm_OsSpecific.h"      // Defines interesting virtual base addresses of interesting register sets on a per-OS basis
#include "xllp_Pm_SleepContext.h"
#include "MEMDefs.h"
#include "pmgr.h"

#ifndef BSP_NOIPM
#include "IPM_Kern.h"
#endif




#pragma pack (1)


// these are defined in cache.s (ASM routines)
extern void FlushDCache(void);
extern void FlushICache(void);
extern void TLBClear(void);
extern UINT32 XSC1GetCPSR(void);
// debug.c
void OsSpecificDebugCommsResume(void);
void OEMInitDebugSerialKernel (void) ;

extern BOOL IPM_RegisterWakeUpReasons();


// locally defined

static P_XLLP_PM_ENTER_SLEEP_PARAMS_T pPmgrSleepParams ;
static volatile P_PM_SLEEP_DATA_T pPmSleepData;
static volatile P_XLLP_PM_ENTER_SLEEP_PARAMS_T pSlpParams;


//------------------------
#ifdef  BUILDING_SAMPLE_OPT_REGLIST

    XLLP_PM_ADDR_WITH_MASK_T PmRegList [PM_OPTIONAL_REGLIST_SIZE] =
    {
        // PGSRx regs will be restored, but must be modified before being saved
        {&regListTestJunkArray[0],          0XFFFFFFFF} ,
        {&regListTestJunkArray[1],          0XFFFFFFFF} ,
        {&regListTestJunkArray[2],          0XFFFFFFFF} ,
        {&regListTestJunkArray[3],          0XFFFFFFFF} 

    }; // PmRegList

#endif // def  BUILDING_SAMPLE_OPT_REGLIST
//------------------------


//-----------------
void OEMPowerOff (void)
{
   PMEMC pv_memc = (PMEMC) MEMC_BASE_U_VIRTUAL;
    

    #ifdef DBG_NO_HW_SR
        // This debug #define is intended to stub out OEMPowerOff(), including
        //   processor sleep and reset as well as low-level register save/restore
        return;
    #endif // def DBG_NO_HW_SR

    pPmSleepData = (volatile P_PM_SLEEP_DATA_T) SLEEP_SAVE_U_VIRTUAL;

// Need to use this space because of permissions.
    pPmgrSleepParams =  &pPmSleepData->sleepParameters;

    // Set up parameter for Xllp context save-restore
    // Eventually, this will become an initialized variable that is modified 
    //  during run time to reflect current system options.
// Doing only for non-sleep resets.
// see OEMInit().    PmgrInitSleepParam(pPmgrSleepParams);


// CJW tmp.  Force clear of MDREFR[K2DB2]
    pv_memc->mdrefr &= ~(0x00080000u );/*xlli_MDREFR_K2DB2*/

    // Sleep and return
    XllpPmEnterSleep (pPmgrSleepParams);

    // Dump the OSCR values if desired and measuring.
//cjw    PmgrDumpOSCRs();

} // OEMPowerOff()


    // This sets and restores the default sleep parameter values.
    
XLLP_STATUS_T PmgrInitSleepParam(PVOID pvu_SleepAreaBase,
                                 BOOL forceReset) // Unless forced, skips init if done.
{
    // This is now a public function, so we need to derive the address for the 
    //  sleep parameters structure.

    volatile P_PM_SLEEP_DATA_T pPmSleepData =
                                (volatile P_PM_SLEEP_DATA_T) pvu_SleepAreaBase;
    volatile XLLP_OST_T *pv_pOSTReg  = (volatile XLLP_OST_T*) OST_BASE_U_VIRTUAL;
    P_XLLP_PM_ENTER_SLEEP_PARAMS_T  pSlpParams = &pPmSleepData->sleepParameters;
    XLLP_STATUS_T status = XLLP_STATUS_SUCCESS;
//  NKDbgPrintfW(TEXT("+PmgrInitSleepParam\r\n"));

    if (!pvu_SleepAreaBase)
    {
        status = XLLP_STATUS_WRONG_PARAMETER;
    }
    else 
    {
// NKDbgPrintfW(TEXT("++PmgrInitSleepParam\r\n"));
        if ((!pSlpParams->SleepDataAreaPA)||forceReset)
        {
        // Need to use this space because of permissions.
            pSlpParams =  &pPmSleepData->sleepParameters;

            // Force any unsupported options to not-selected.
            memset (pSlpParams, 0, sizeof (XLLP_PM_ENTER_SLEEP_PARAMS_T));  // addr, value, size

            pSlpParams->SleepDataAreaPA =  (XLLP_UINT32_T) SLEEP_SAVE_PHYSICAL;
            pSlpParams->SleepDataAreaVA =  (P_XLLP_PM_SLEEP_SAVE_DATA_T) SLEEP_SAVE_U_VIRTUAL;
            pSlpParams->pTmpStack = NULL;   // Stack not in internal memory.
            pSlpParams->Addr_EndSleepTime    = &pSlpParams->EndSleepTime;  // Not in IM.
            pSlpParams->OSCR_Addr            = (P_XLLP_UINT32_T)&(pv_pOSTReg->oscr0);
            pSlpParams->SleepOptions         = PMGR_SleepOptions_DFLT;
            pSlpParams->LowPowerModeSelect   = PMGR_LowPowerModeSelect_DFLT;
            pSlpParams->pOsSpecificFlushFn   = PmgrProcessorFlushAll;
            pSlpParams->pOsSuspendOptionalFn = PmgrOsSuspendOptionalFn;
            pSlpParams->pOsResumeOptionalFn  = PmgrOsResumeOptionalFn;
            pSlpParams->CKEN_msk    =   PMGR_CKEN_msk_DFLT;   
            pSlpParams->CKEN_vals   =   PMGR_CKEN_vals_DFLT ;// no specials needed for B0? | XLLP_CLKEN_OST;

#ifdef BSP_NOIPM
			pSlpParams->PGSR0_msk   =   PMGR_PGSR0_msk_DFLT;   
            pSlpParams->PGSR1_msk   =   PMGR_PGSR1_msk_DFLT;   
            pSlpParams->PGSR2_msk   =   PMGR_PGSR2_msk_DFLT;   
            pSlpParams->PGSR3_msk   =   PMGR_PGSR3_msk_DFLT;   
            pSlpParams->PGSR0_vals  =   PMGR_PGSR0_vals_DFLT;  
            pSlpParams->PGSR1_vals  =   PMGR_PGSR1_vals_DFLT;  
            pSlpParams->PGSR2_vals  =   PMGR_PGSR2_vals_DFLT;  
            pSlpParams->PGSR3_vals  =   PMGR_PGSR3_vals_DFLT;  
#if 0	//hzh
            pSlpParams->PWER  =   0x80000002u; // PMGR_PWER_DFLT;  // Wake for RTC alarm or GPIO1
            pSlpParams->PRER  =   2u;// PMGR_PRER_DFLT;
            pSlpParams->PFER  =   2u;// PMGR_PFER_DFLT;
#else
            pSlpParams->PWER  =   0x80000001u; // PMGR_PWER_DFLT;  // Wake for RTC alarm or GPIO0
            pSlpParams->PRER  =   0u;// PMGR_PRER_DFLT;
            pSlpParams->PFER  =   1u;// PMGR_PFER_DFLT;
#endif
            pSlpParams->PKWR  =   0x0u; // PMGR_PKWR_DFLT;
#else
            pSlpParams->PGSR0_msk   =   PMGR_PGSR0_msk_DFLT;   
            pSlpParams->PGSR1_msk   =   PMGR_PGSR1_msk_DFLT;   
            pSlpParams->PGSR2_msk   =   PMGR_PGSR2_msk_DFLT;   
            pSlpParams->PGSR3_msk   =   PMGR_PGSR3_msk_DFLT | 0x00001F81;   
            pSlpParams->PGSR0_vals  =   PMGR_PGSR0_vals_DFLT;  
            pSlpParams->PGSR1_vals  =   PMGR_PGSR1_vals_DFLT;  
            pSlpParams->PGSR2_vals  =   PMGR_PGSR2_vals_DFLT;  
            pSlpParams->PGSR3_vals  =   PMGR_PGSR3_vals_DFLT | 0x00001F81;  
            pSlpParams->PWER  =   0x80000000u; // PMGR_PWER_DFLT;  // Wake for RTC alarm or GPIO1
            pSlpParams->PRER  =   0x0u;// PMGR_PRER_DFLT;
            pSlpParams->PFER  =   0x0u;// PMGR_PFER_DFLT;
            pSlpParams->PKWR  =   0x000FD000u; // PMGR_PKWR_DFLT;
#endif

            // PCFR
            //   (En/Disable 32MHz osc, force/float PCMCIA and nCS lines, etc.)
            // Forcing certain values in PCFR for now, leaving some and zeroing reserved bits
            //    (AND mask for reserved bits to force low (31:13, 9:8, 3): 0x00001CF7)
            //    (AND mask for values to force low (L1_EN[11], DC_EN[7], FS[2], FP[1]):
            //                ~(0x00000886))
            //    (OR mask for values to force high (SYSEN_EN[5]) = 0x020)

            // Do not enable RDH_OVERRIDE or PH_OVERRIDE (1u << 15, 1u << 14).  
            //    - Maintain PXA2xx + Bulverde An behavior.
            // Do not suppress nReset out during GPIO reset (suppress = 1u << 12)
            //    - On Mainston I+II, nReset out is used to reset FPGA., so not used for sleep.
            // Don't use the Pwr I2C during sleep (enable = 1u << 6)