stack3.vhd

设计ip协议的vhdl实现

		clk => clk,
		rstn => rstn,
		RX_DATA => rxdata,
		RX_DV => rx_dv,
		RX_CLK => rx_clk_buf,
		frameType => frameTypeRec,
		frameByte => newFrameByte,
		frameData => frameData,
		newFrame => newframe,
		endFrame => endFrame,
		frameValid => frameValid
	);
	
	-- instantiantion of the ethernet sender component 
	MASSnd : ethernetSnd port map (
        clk => clk,
        rstn => rstn,
        complete => RAMCompleteEthSnd,
        rdData => rdData,
        newFrame => sendFrameARP,
        frameSize => frameLenARP,
        destinationMAC => destinationMAC,
        frameType => frameTypeSend,
        TX_CLK => tx_clk_buf,
        TX_EN => tx_en,
        TX_DATA => txdata,
        rdRAM => rdRAMEthSnd,
        rdAddr => rdAddrEthSnd,
        frameSent => frameSentEth
    );

	-- instantiantion of the ARP component 
	ARPTable : ARP port map (
		clk => clk,
		rstn => rstn,
		newFrame => newFrame,
		frameType => frameTypeREC,
		newFrameByte => newFrameByte,
		frameData => frameData,
		endFrame => endFrame,
		frameValid => frameValid,
		ARPSendAvail => ARPSendAvail,
		requestIP => requestIP,
		genARPRep => genARPRep,
		genARPIP => genARPIP,
		lookupMAC => lookupMAC,
		validEntry => validEntry
    );

	-- instantiantion of the ARP request / reply sender component 
	ARPSender : ARPSnd port map (
        clk => clk,
        rstn => rstn,
        complete => RAMCompleteARPSnd,
        frameSent => frameSentEth,
        sendFrame => sendFrame,
        frameLen => frameSize,
        targetIP => ARPIP,
        ARPEntryValid => validEntry,
        genARPReply => genARPRep,
        genARPIP => genARPIP,
        lookupMAC => lookupMAC,
        lookupIP => requestIP,
        sendingReply => ARPSendAvail,
        targetMAC => destinationMAC,
        genFrame => sendFrameARP,
        frameType => frameTypeSend,
        frameSize => frameLenARP,
        idle => open,
        sendingFrame => frameSent,
        wrRAM => wrRAMARPSnd,
        wrData => wrDataARPSnd,
        wrAddr => wrAddrARPSnd
    );
    
	-- instantiantion of the internet datagram receiver component 
	networkLayer : internet port map (
		clk => clk,
		rstn => rstn,
		complete => RAMCompleteNet,
		newFrame => newFrame,
		frameType => frameTypeRec,
		newFrameByte => newFrameByte,
		frameData => frameData,
		endFrame => endFrame,
		frameValid => frameValid,
		newDatagram => newDatagram,
		bufferSelect => bufferSelect,
		datagramSize => datagramSize,
		protocol => protocolRec,
		sourceIP => sourceIP,
		wrRAM => wrRAMNet,
		wrData => wrDataNet,
		wrAddr => wrAddrNet,
		timeLED0 => bar(2),
		timeLED1 => bar(3)
    );

	-- instantiantion of the internet datagram sender component 
	networkLayerSend: InternetSnd port map(
        clk => clk,
        rstn => rstn,
        frameSent => frameSent,
        sendDatagram => sendDatagram,
        datagramSize => sendDatagramSize,
        destinationIP => destinationIP,
        addressOffset => addressOffset,
        protocol => protocolSend,
        complete => RAMCompleteNetSnd,
        rdData => rdData,
        rdRAM => rdRAMNetSnd,
        rdAddr => rdAddrNetSnd,
        wrRAM => wrRAMNetSnd,
        wrData => wrDataNetSnd,
        wrAddr => wrAddrNetSnd,
        sendFrame => sendFrame,
        datagramSent => open,
        frameSize => frameSize,
        ARPIP => ARPIP
    );
    
	-- instantiantion of the UDP receiver component 
	UDPtransportLayer: udp port map (
		clk => clk,
		rstn => rstn,
		protocol => protocolRec,
		newDatagram => newDatagram,
		sourceIP => sourceIP,
		IPbuffer => bufferSelect,
		complete => RAMCompleteUDP,
		rdData => rdData,
		rdRAM => rdRAMUDP,
		rdAddr => rdAddrUDP,
		wrRAM => wrRAMUDP,
		wrData => wrDataUDP,
		wrAddr => wrAddrUDP,
		sourceIPOut => open
    );
    
    
	-- instantiantion of the ICMP protocol component
	ICMPtransportLayer: ICMP port map (
        clk => clk,
        rstn => rstn,
        newDatagram => newDatagram,
        datagramSize => datagramSize,
        bufferSelect => bufferSelect,
   		protocolIn => protocolRec,
		sourceIP => sourceIP,
        complete => RAMCompleteTrans,
        rdData => rdData,
        rdRAM => rdRAMTrans,
        rdAddr => rdAddrTrans,
        wrRAM => wrRAMTrans,
        wrData => wrDataTrans,
        wrAddr => wrAddrTrans,
        sendDatagramSize => sendDatagramSize,
        sendDatagram => sendDatagram,
        destinationIP => destinationIP,
        addressOffset => addressOffset,
        protocolOut => protocolSend
    );

	-- instantiantion of the SRAM component
	SRAMInterface : sraminterfacewithpport port map (
        clk => clk,
        Resetn => rstn,
        doRead => rdRAM,
        doWrite => wrRAM,
        readAddr => rdAddr,
        writeAddr => wrAddr,
        readData (15 downto 8) => open,
        readData (7 downto 0) => rdData,
        writeData (15 downto 8) => waste,
        writeData (7 downto 0) => wrData,
        canRead => open,
        canWrite => canWrite,
        CELeftn => lcen,
        OELeftn => loen,
        WELeftn => lwen,
        SRAMLeftAddr => laddr,
        SRAMLeftData => ldata,
        ppdata => ppdata,
        ppstatus => ppstatus
    );
    
	-- clock buffer for RX_CLOCK
	rx_clkBuff : bufg port map (
		I => rx_clk,
		O => rx_clk_buf
	);

	-- clock buffer for TX_CLOCK
	tx_clkBuff : bufg port map (
		I => tx_clk,
		O => tx_clk_buf
	);

	-- hardwire TX_ER, mdc, mdio and trste to low - none of these are used
	tx_er <= '0';
	mdc <= '0';
	mdio <= '0';
	trste <= '0';

	-- waste signal - useless
	waste <= (others => '0');


	-- RAM arbitration for the whole project
	-- main clocked process
	process(clk,rstn)
	begin
		if rstn = '0' then
			presState <= stIdle;
		elsif clk'event and clk = '1' then
			presState <= nextState;
		end if;
	end process;
			
	-- FSM process
	process (presState, wrRAMNet, wrDataNet, wrAddrNet, rdRAMTrans, rdAddrTrans, wrRAMTrans, 
			wrDataTrans, canWrite, wrAddrTrans, rdRAMNetSnd, rdAddrNetSnd, wrRAMNetSnd, wrDataNetSnd, 
			wrAddrNetSnd, wrRAMARPSnd, wrRAMARPSnd, wrDataARPSnd, wrAddrARPSnd, rdAddrEthSnd, rdRAMEthSnd,
			rdRAMUDP, rdAddrUDP, wrRAMUDP, wrDataUDP, wrAddrUDP)
	begin
		-- if we can write or read, then allow whoever requests it and multiplex the RAM lines
		if presState = stIdle or canWrite = '1' then
			-- giving ethernet send priority...
			if rdRAMEthSnd = '1' then
				nextState <= stServicingEthSnd;
				wrRAM <= '0';
				rdRAM <= rdRAMEthSnd;
				wrData <= (others => '0');
				wrAddr <= (others => '0');
				rdAddr <= rdAddrEthSnd;
			elsif wrRAMARPSnd = '1' then
				nextState <= stServicingARPSnd;
				wrRAM <= wrRAMARPSnd;
				rdRAM <= '0';
				wrData <= wrDataARPSnd;
				wrAddr <= wrAddrARPSnd;
				rdAddr <= (others => '0');
			elsif wrRAMNet = '1' then
				nextState <= stServicingNet;
				wrRAM <= wrRAMNet;
				rdRAM <= '0';
				wrData <= wrDataNet;
				wrAddr <= wrAddrNet;
				rdAddr <= (others => '0');
			elsif wrRAMTrans = '1' or rdRAMTrans = '1' then
				nextState <= stServicingTrans;			
				wrRAM <= wrRAMTrans;
				rdRAM <= rdRAMTrans;
				wrData <= wrDataTrans;
				wrAddr <= wrAddrTrans;
				rdAddr <= rdAddrTrans;
			elsif wrRAMNetSnd = '1' or rdRAMNetSnd = '1' then
				nextState <= stServicingNetSnd;
				wrRAM <= wrRAMNetSnd;
				rdRAM <= rdRAMNetSnd;
				wrData <= wrDataNetSnd;
				wrAddr <= wrAddrNetSnd;
				rdAddr <= rdAddrNetSnd;
			elsif wrRAMUDP = '1' or rdRAMUDP = '1' then
				nextState <= stServicingUDP;
				wrRAM <= wrRAMUDP;
				rdRAM <= rdRAMUDP;
				wrData <= wrDataUDP;
				wrAddr <= wrAddrUDP;
				rdAddr <= rdAddrUDP;
			else
				nextState <= stIdle; 
				wrRAM <= '0';
				rdRam <= '0';
				wrData <= (others => '0');
				wrAddr <= (others => '0');
				rdAddr <= (others => '0');
			end if;			
		else
			nextState <= presState; 
			wrRAM <= '0';
			rdRAM <= '0';
			wrData <= (others => '0');
			wrAddr <= (others => '0');
			rdAddr <= (others => '0');			
		end if;

		-- connect the RAM complete signal to each state which requested it when needed
		case presState is
			when stIdle =>
				RAMcompleteNet <= '0';
				RAMcompleteTrans <= '0';
				RAMcompleteNetSnd <= '0';
				RAMcompleteEthSnd <= '0';
				RAMcompleteARPSnd <= '0';
				RAMcompleteUDP <= '0';
			when stServicingNet =>
				RAMcompleteNet <= canWrite;
				RAMcompleteTrans <= '0';
				RAMcompleteNetSnd <= '0';
				RAMcompleteEthSnd <= '0';
				RAMcompleteARPSnd <= '0';
				RAMcompleteUDP <= '0';
			when stServicingTrans =>
				RAMcompleteNet <= '0';
				RAMcompleteTrans <= canWrite;
				RAMcompleteNetSnd <= '0';
				RAMcompleteEthSnd <= '0';
				RAMcompleteARPSnd <= '0';
				RAMcompleteUDP <= '0';
			when stServicingNetSnd =>
				RAMcompleteNet <= '0';
				RAMcompleteTrans <= '0';
				RAMcompleteNetSnd <= canwrite;
				RAMcompleteEthSnd <= '0';
				RAMcompleteARPSnd <= '0';
				RAMcompleteUDP <= '0';
			when stServicingEthSnd =>
				RAMcompleteNet <= '0';
				RAMcompleteTrans <= '0';
				RAMcompleteNetSnd <= '0';
				RAMcompleteEthSnd <= canWrite;
				RAMcompleteARPSnd <= '0';
				RAMcompleteUDP <= '0';
			when stServicingARPSnd =>
				RAMcompleteNet <= '0';
				RAMcompleteTrans <= '0';
				RAMcompleteNetSnd <= '0';
				RAMcompleteEthSnd <= '0';
				RAMcompleteARPSnd <= canWrite;
				RAMcompleteUDP <= '0';
			when stServicingUDP =>
				RAMcompleteNet <= '0';
				RAMcompleteTrans <= '0';
				RAMcompleteNetSnd <= '0';
				RAMcompleteEthSnd <= '0';
				RAMcompleteARPSnd <= '0';
				RAMcompleteUDP <= canWrite;
			when others =>
				RAMcompleteNet <= '0';
				RAMcompleteTrans <= '0';
				RAMcompleteNetSnd <= '0';
				RAMcompleteEthSnd <= '0';
				RAMcompleteARPSnd <= '0';
				RAMcompleteUDP <= '0';
		end case;	
	end process;							
end stack_arch;