updown2.vhd

CPLDFPGA嵌入式应用开发技术白金手册

-- updown2 模块(of testup_f_k)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity updown2 is
 port(
       r_in:in std_logic;
       key:in std_logic;
       s_in:in std_logic;
       sys_clk:in std_logic;
       addr_f: out std_logic_vector(6 downto 0);
       led:out std_logic_vector(1 downto 0);
       dataout:out std_logic_vector(9 downto 0));
 end updown2;
 architecture behave of updown2 is
 signal clk:std_logic;
 signal data:std_logic_vector(9 downto 0);
 signal count: std_logic_vector(6 downto 0);
begin
process(sys_clk)
     begin
     if sys_clk'event and sys_clk='0' then
       clk<=(r_in and s_in);
     end if;
 end process;
 process(clk)
     begin
           if clk'event and clk='0' then
                 if key='1' then
                       if(count<127) then
                          count<=count+1;
                          if data<"0010000000" then
                                 data<=data+2;
                          else data<=data+14;
                          end if;
                       end if;
                   else
                      if (count>0) then
                          count<=count-1;
                      	if data<="0010000000" and data>"0000000000" then
                            data<=data-2;
                        else  data<=data-14;
                      end if;
                   end if;
                 end if;
           end if;
end process;
   process(count)
       begin
          if count="1111111" then led<="11";
          elsif count>"1110001" and count<"1111111"	then
				   led<="10";
          elsif count<"1110010" and count>"0110100" then
			 led<="01";
                   else led<="00";
                   end if;
       end process;
          dataout<=data;
          addr_f<=count;
 end behave;