division10.vhd

CPLDFPGA嵌入式应用开发技术白金手册

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity division10 is
port(lin:in std_logic_vector(9 downto 0);
	 clock:in std_logic;
	 lout:out std_logic
	);
end division10;

architecture beh of division10 is
begin
 process(clock)
  variable count:std_logic_vector(9 downto 0);
  variable ll:std_logic;
	begin
  	  if clock'event and clock='0' then
		if(count<lin) then
	        ll:='0';
			count:=count+'1';
		elsif(count>=lin) then
			ll:='1';
			count:="0000000000";
		end if;
     end if;
lout<=ll;
end process;
end beh;