sanjiao.vhd

CPLDFPGA嵌入式应用开发技术白金手册

--sanjiao 模块
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 entity sanjiao is
 port(
    clk   :in std_logic;
    dout  : out std_logic_vector(5 downto 0)
   );
 end sanjiao;
architecture behav of sanjiao is
begin
     process(clk)
     variable count:std_logic_vector(5 downto 0);
     begin
           if clk'event and clk='0' then
                  count:=count+1;
                  dout<=count;
           end if;
     end process;
end behav;