lut_a_f.vhd

CPLDFPGA嵌入式应用开发技术白金手册

--lut_a_f
library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity lut_a_f is
      port (addr:in std_logic_vector(7 downto 0);
            outdata:out std_logic_vector(11 downto 0);
            cLk:in std_logic);
end lut_a_f;

architecture lut_arc of lut_a_f is
component LPM_ROM
generic (LPM_WIDTH:natural;
           LPM_WIDTHAD:NATURAL;
           LPM_NUMWORDS:natural:=0;
 		   LPM_ADDRESS_CONTROL:string:="REGISTERED";
		   LPM_OUTDATA:string:="REGISTERED";
 		   LPM_FILE:string;
 		   LPM_TYPE:string:=" LPM_ROM";
		   LPM_HINT:string:="UNUSED");
port(ADDRESS: in std_logic_vector(LPM_WIDTHAD-1 downto 0);
       INCLOCK:in STD_LOGIC:='0';
       OUTCLOCK:in STD_LOGIC:='0';
       Q:out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
begin
ul:lpm_rom 
generic map(12,8,0,"registered","unregistered","aaf.mif","lpm_rom","unused")
port map(inclock=>clk,address=>addr, q=>outdata);
end lut_arc;