mul_8.vhd

CPLDFPGA嵌入式应用开发技术白金手册

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity mul_8 is        --接口
   port(clk:in std_logic;
          x:in integer range -128 to 127;
          a:in std_logic_vector(7 downto 0);
          y:out integer range -32768 to 32767);
end mul_8;

architecture bit of mul_8 is
   type state_type is(s1,s2,s3);
   signal state:state_type;
begin
     beh:process           --行为描述
          variable p,t: integer range -32768 to 32767;
          variable count : integer range 0 to 7;
     begin
        wait until clk='1';
        case state is
        when s1=>state<=s2;     --第1步初始化
                 count:=0;  
		         p:=0;          --重置寄存器
		         t:=x;          --移位
	    when s2=>if count=7 then
                    state<=s3;
                   else 
		             if a(count)='1' then
                       p:=p+1;
                   end if;
                   t:=t*2;
                   count:=count+1;
                   state<=s2;
                 end if;
        when s3=>y<=p;
                 state<=s1;
        end case;
  end process beh;
end bit;