reg4.vhd

CPLDFPGA嵌入式应用开发技术白金手册

Library IEEE ;
use IEEE.std_logic_1164.all ;


ENTITY reg4 IS
	PORT(
		d:in std_logic_vector(3 downto 0);
		ci: IN std_logic;	
		clk		: IN   std_logic;
		q:out std_logic_vector(3 downto 0);
		co: out std_logic);
END reg4;

ARCHITECTURE a OF reg4 IS
BEGIN
	PROCESS
	BEGIN
		WAIT UNTIL clk = '1';
		q <= d;
		co <= ci;
	END PROCESS;
END a;