flash.vhd

来自「CPLDFPGA嵌入式应用开发技术白金手册」· VHDL 代码 · 共 40 行

--flash
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity flash is
port(clk,en:in std_logic;
     beam:in std_logic_vector(6 downto 0);
     q6,q5,q4,q3,q2,q1,q0:out std_logic);
end flash;
architecture rtl of flash is
begin
  process(en,beam)
   begin
    if(en='0') then
     if(clk='0') then
q6<='1';q5<='1';q4<='1';
q3<='1';q2<='1';q1<='1';q0<='1';
     else
q6<=beam(6) ;
q5<=beam(5);
q4<=beam(4);
q3<=beam(3);
q2<=beam(2);
q1<=beam(1);
q0<=beam(0);
     end if;    
   else
q6<=beam(6);
q5<=beam(5);
q4<=beam(4);
q3<=beam(3);
q2<=beam(2);
q1<=beam(1);
q0<=beam(0);
  end if;
end process;
end rtl;