firfilter.vhd

来自「CPLDFPGA嵌入式应用开发技术白金手册」· VHDL 代码 · 共 33 行

package eight_bit_int is    --用户定义类型
subtype fbyte is integer range -128 to 127;
type array_byte is array(0 to 3)of fbyte;
end eight_bit_int;

library work;
use work.eight_bit_int.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity firfilter is
    port(clk :in std_logic;
         x: in fbyte;
         y: out fbyte);
  end firfilter;

architecture fir of firfilter is
   signal t:array_byte;     --抽头延迟线tapped
   
begin
   p1:process
   begin
     wait until clk='1';
     y<=2*t(1)+t(1)+t(1)/2+t(1)/4+2*t(2)+t(2)+t(2)/2+t(2)/4-t(3)-t(0);
     for i in 3 downto 1 loop
     t(i)<=t(i-1);
   end loop;
   t(0)<=x;
  end process;
end fir;