reg32bit.vhd

CPLDFPGA嵌入式应用开发技术白金手册

library ieee;
use ieee.std_logic_1164.all;

entity reg32bit is
  port(load:in std_logic;
	din:in std_logic_vector(31 downto 0);
	dout:out std_logic_vector(31 downto 0));
end reg32bit;

architecture beh of reg32bit is
  begin
    process(load,din)
      begin
	if load'event and load='1' then
	   dout<=din;
	end if;
    end process;
end beh;