acquisition_theoretic.mdl
来自「本人做的GPS整个基带的捕获模型.用的是SIMULINK,捕获方式采用码并行捕获」· MDL 代码 · 共 2,298 行 · 第 1/5 页
MDL
2,298 行
Name "corr result"
Position [765, 58, 795, 72]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Real-Imag to\nComplex2"
SrcPort 1
DstBlock "Buffer"
DstPort 1
}
Line {
SrcBlock "Q"
SrcPort 1
Points [35, 0; 0, -15]
DstBlock "Real-Imag to\nComplex2"
DstPort 2
}
Line {
SrcBlock "I"
SrcPort 1
DstBlock "Real-Imag to\nComplex2"
DstPort 1
}
Line {
SrcBlock "Zero Pad"
SrcPort 1
DstBlock "FFT1"
DstPort 1
}
Line {
SrcBlock "Zero Pad1"
SrcPort 1
DstBlock "FFT"
DstPort 1
}
Line {
SrcBlock "Abs"
SrcPort 1
DstBlock "corr result"
DstPort 1
}
Line {
SrcBlock "FFT1"
SrcPort 1
DstBlock "Math\nFunction1"
DstPort 1
}
Line {
SrcBlock "FFT"
SrcPort 1
DstBlock "Product"
DstPort 1
}
Line {
SrcBlock "Math\nFunction1"
SrcPort 1
Points [10, 0; 0, -55]
DstBlock "Product"
DstPort 2
}
Line {
SrcBlock "Product"
SrcPort 1
DstBlock "IFFT"
DstPort 1
}
Line {
SrcBlock "Buffer"
SrcPort 1
DstBlock "Zero Pad1"
DstPort 1
}
Line {
SrcBlock "Buffer1"
SrcPort 1
DstBlock "Zero Pad"
DstPort 1
}
Line {
SrcBlock "IFFT"
SrcPort 1
DstBlock "Abs"
DstPort 1
}
Line {
SrcBlock "Real-Imag to\nComplex1"
SrcPort 1
DstBlock "Buffer1"
DstPort 1
}
Line {
SrcBlock "local_I"
SrcPort 1
DstBlock "Real-Imag to\nComplex1"
DstPort 1
}
Line {
SrcBlock "local_Q"
SrcPort 1
Points [35, 0; 0, -20]
DstBlock "Real-Imag to\nComplex1"
DstPort 2
}
}
}
Block {
BlockType FrameConversion
Name "2Frame"
Position [325, 60, 380, 100]
OutFrame "Frame based"
}
Block {
BlockType FrameConversion
Name "2Frame1"
Position [325, 190, 380, 230]
OutFrame "Frame based"
}
Block {
BlockType Reference
Name "AWGN\nChannel"
Ports [1, 1]
Position [580, 51, 675, 109]
SourceBlock "commchan3/AWGN\nChannel"
SourceType "AWGN Channel"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
seed "55"
noiseMode "Signal to noise ratio (SNR)"
EbNodB "0"
EsNodB "10"
SNRdB "0"
bitsPerSym "1"
Ps "1"
Tsym "1"
variance "1"
}
Block {
BlockType Reference
Name "AWGN\nChannel1"
Ports [1, 1]
Position [580, 181, 675, 239]
SourceBlock "commchan3/AWGN\nChannel"
SourceType "AWGN Channel"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
seed "67"
noiseMode "Signal to noise ratio (SNR)"
EbNodB "0"
EsNodB "10"
SNRdB "0"
bitsPerSym "1"
Ps "1"
Tsym "1"
variance "1"
}
Block {
BlockType Sum
Name "Add"
Ports [2, 1]
Position [870, 72, 900, 103]
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "BPSK\nModulator\nBaseband"
Ports [1, 1]
Position [215, 56, 290, 104]
SourceBlock "commdigbbndpm3/BPSK\nModulator\nBaseband"
SourceType "BPSK Modulator Baseband"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Ph "0"
outDtype "double"
outWordLen "16"
outUDDataType "sfix(16)"
outFracLenMode "Best precision"
outFracLen "15"
}
Block {
BlockType Reference
Name "BPSK\nModulator\nBaseband1"
Ports [1, 1]
Position [215, 186, 290, 234]
SourceBlock "commdigbbndpm3/BPSK\nModulator\nBaseband"
SourceType "BPSK Modulator Baseband"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Ph "pi/4"
outDtype "double"
outWordLen "16"
outUDDataType "sfix(16)"
outFracLenMode "Best precision"
outFracLen "15"
}
Block {
BlockType ComplexToRealImag
Name "C2RI"
Ports [1, 2]
Position [365, 328, 395, 357]
Output "Real and imag"
}
Block {
BlockType ComplexToRealImag
Name "C2RI1"
Ports [1, 2]
Position [365, 498, 395, 527]
Output "Real and imag"
}
Block {
BlockType ComplexToRealImag
Name "C2RI2"
Ports [1, 2]
Position [365, 543, 395, 572]
Output "Real and imag"
}
Block {
BlockType SubSystem
Name "Ci(t)"
Ports [0, 1]
Position [35, 15, 105, 75]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
MaskPromptString "Enter PRN"
MaskStyleString "edit"
MaskTunableValueString "on"
MaskEnableString "on"
MaskVisibilityString "on"
MaskToolTipString "on"
MaskVariables "prn=@1;"
MaskDisplay "fprintf('C/A Code\\nGenerator\\nPRN = %2d',prn)"
";"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
MaskValueString "1"
System {
Name "Ci(t)"
Location [47, 238, 478, 334]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Reference
Name "1.023MHz"
Ports [0, 1]
Position [25, 33, 70, 67]
SourceBlock "gpsSim/clock"
SourceType "Digital clock"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
T "1/1.023e6"
}
Block {
BlockType Reference
Name "C/A generator"
Ports [1, 1]
Position [130, 34, 200, 66]
SourceBlock "gpsSim/C//A generator"
SourceType "C/A code generator"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
prn "prn"
}
Block {
BlockType Outport
Name "Out1"
Position [360, 43, 390, 57]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "1.023MHz"
SrcPort 1
Points [0, 0]
DstBlock "C/A generator"
DstPort 1
}
Line {
SrcBlock "C/A generator"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "Ci(t)1"
Ports [0, 1]
Position [35, 175, 105, 235]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
MaskPromptString "Enter PRN"
MaskStyleString "edit"
MaskTunableValueString "on"
MaskEnableString "on"
MaskVisibilityString "on"
MaskToolTipString "on"
MaskVariables "prn=@1;"
MaskDisplay "fprintf('C/A Code\\nGenerator\\nPRN = %2d',prn)"
";"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
MaskValueString "10"
System {
Name "Ci(t)1"
Location [47, 238, 478, 334]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Reference
Name "1.023MHz"
Ports [0, 1]
Position [25, 33, 70, 67]
SourceBlock "gpsSim/clock"
SourceType "Digital clock"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
T "1/1.023e6"
}
Block {
BlockType Reference
Name "C/A generator"
Ports [1, 1]
Position [130, 34, 200, 66]
SourceBlock "gpsSim/C//A generator"
SourceType "C/A code generator"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
prn "prn"
}
Block {
BlockType Outport
Name "Out1"
Position [360, 43, 390, 57]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "C/A generator"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "1.023MHz"
SrcPort 1
Points [0, 0]
DstBlock "C/A generator"
DstPort 1
}
}
}
Block {
BlockType Reference
Name "Clock"
Ports [0, 1]
Position [30, 601, 70, 629]
SourceBlock "simulink_extras/Flip Flops/Clock"
SourceType "Digital clock"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
MaskParam1 "1/1.023e6"
}
Block {
BlockType Reference
Name "Clock1"
Ports [0, 1]
Position [30, 421, 70, 449]
SourceBlock "simulink_extras/Flip Flops/Clock"
SourceType "Digital clock"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
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