📄 au1000.txt
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319 #define PC0_TRIM (PC_BASE + 0)
320 #define PC0_COUNTER_WRITE (PC_BASE + 4)
321 #define PC0_MATCH0 (PC_BASE + 8)
322 #define PC0_MATCH1 (PC_BASE + 0xC)
323 #define PC0_MATCH2 (PC_BASE + 0x10)
324 #define PC0_COUNTER_READ (PC_BASE + 0x40)
325
326 /* Programmable Counter 1 Registers */
327 #define PC1_TRIM (PC_BASE + 0x44)
328 #define PC1_COUNTER_WRITE (PC_BASE + 0x48)
329 #define PC1_MATCH0 (PC_BASE + 0x4C)
330 #define PC1_MATCH1 (PC_BASE + 0x50)
331 #define PC1_MATCH2 (PC_BASE + 0x54)
332 #define PC1_COUNTER_READ (PC_BASE + 0x58)
333
334
335 /* I2S Controller */
336 #define I2S_DATA 0x11000000
337 #define I2S_CONFIG_STATUS 0x11000001
338 #define I2S_CONTROL 0x11000002
339
340 /* Ethernet Controllers */
341 #define AU1000_ETH0_BASE 0x10500000
342 #define AU1000_ETH1_BASE 0x10510000
343
344 /* 4 byte offsets from AU1000_ETH_BASE */
345 #define MAC_CONTROL 0x0
346 #define MAC_RX_ENABLE (1<<2)
347 #define MAC_TX_ENABLE (1<<3)
348 #define MAC_DEF_CHECK (1<<5)
349 #define MAC_SET_BL(X) (((X)&0x3)<<6)
350 #define MAC_AUTO_PAD (1<<8)
351 #define MAC_DISABLE_RETRY (1<<10)
352 #define MAC_DISABLE_BCAST (1<<11)
353 #define MAC_LATE_COL (1<<12)
354 #define MAC_HASH_MODE (1<<13)
355 #define MAC_HASH_ONLY (1<<15)
356 #define MAC_PASS_ALL (1<<16)
357 #define MAC_INVERSE_FILTER (1<<17)
358 #define MAC_PROMISCUOUS (1<<18)
359 #define MAC_PASS_ALL_MULTI (1<<19)
360 #define MAC_FULL_DUPLEX (1<<20)
361 #define MAC_NORMAL_MODE 0
362 #define MAC_INT_LOOPBACK (1<<21)
363 #define MAC_EXT_LOOPBACK (1<<22)
364 #define MAC_DISABLE_RX_OWN (1<<23)
365 #define MAC_BIG_ENDIAN (1<<30)
366 #define MAC_RX_ALL (1<<31)
367 #define MAC_ADDRESS_HIGH 0x4
368 #define MAC_ADDRESS_LOW 0x8
369 #define MAC_MCAST_HIGH 0xC
370 #define MAC_MCAST_LOW 0x10
371 #define MAC_MII_CNTRL 0x14
372 #define MAC_MII_BUSY (1<<0)
373 #define MAC_MII_READ 0
374 #define MAC_MII_WRITE (1<<1)
375 #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
376 #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
377 #define MAC_MII_DATA 0x18
378 #define MAC_FLOW_CNTRL 0x1C
379 #define MAC_FLOW_CNTRL_BUSY (1<<0)
380 #define MAC_FLOW_CNTRL_ENABLE (1<<1)
381 #define MAC_PASS_CONTROL (1<<2)
382 #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
383 #define MAC_VLAN1_TAG 0x20
384 #define MAC_VLAN2_TAG 0x24
385
386 /* Ethernet Controller Enable */
387 #define MAC0_ENABLE 0x10520000
388 #define MAC1_ENABLE 0x10520004
389 #define MAC_EN_CLOCK_ENABLE (1<<0)
390 #define MAC_EN_RESET0 (1<<1)
391 #define MAC_EN_TOSS (1<<2)
392 #define MAC_EN_CACHEABLE (1<<3)
393 #define MAC_EN_RESET1 (1<<4)
394 #define MAC_EN_RESET2 (1<<5)
395 #define MAC_DMA_RESET (1<<6)
396
397 /* Ethernet Controller DMA Channels */
398
399 #define MAC0_TX_DMA_ADDR 0x14004000
400 #define MAC1_TX_DMA_ADDR 0x14004200
401 /* offsets from MAC_TX_RING_ADDR address */
402 #define MAC_TX_BUFF0_STATUS 0x0
403 #define TX_FRAME_ABORTED (1<<0)
404 #define TX_JAB_TIMEOUT (1<<1)
405 #define TX_NO_CARRIER (1<<2)
406 #define TX_LOSS_CARRIER (1<<3)
407 #define TX_EXC_DEF (1<<4)
408 #define TX_LATE_COLL_ABORT (1<<5)
409 #define TX_EXC_COLL (1<<6)
410 #define TX_UNDERRUN (1<<7)
411 #define TX_DEFERRED (1<<8)
412 #define TX_LATE_COLL (1<<9)
413 #define TX_COLL_CNT_MASK (0xF<<10)
414 #define TX_PKT_RETRY (1<<31)
415 #define MAC_TX_BUFF0_ADDR 0x4
416 #define TX_DMA_ENABLE (1<<0)
417 #define TX_T_DONE (1<<1)
418 #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
419 #define MAC_TX_BUFF0_LEN 0x8
420 #define MAC_TX_BUFF1_STATUS 0x10
421 #define MAC_TX_BUFF1_ADDR 0x14
422 #define MAC_TX_BUFF1_LEN 0x18
423 #define MAC_TX_BUFF2_STATUS 0x20
424 #define MAC_TX_BUFF2_ADDR 0x24
425 #define MAC_TX_BUFF2_LEN 0x28
426 #define MAC_TX_BUFF3_STATUS 0x30
427 #define MAC_TX_BUFF3_ADDR 0x34
428 #define MAC_TX_BUFF3_LEN 0x38
429
430 #define MAC0_RX_DMA_ADDR 0x14004100
431 #define MAC1_RX_DMA_ADDR 0x14004300
432 /* offsets from MAC_RX_RING_ADDR */
433 #define MAC_RX_BUFF0_STATUS 0x0
434 #define RX_FRAME_LEN_MASK 0x3fff
435 #define RX_WDOG_TIMER (1<<14)
436 #define RX_RUNT (1<<15)
437 #define RX_OVERLEN (1<<16)
438 #define RX_COLL (1<<17)
439 #define RX_ETHER (1<<18)
440 #define RX_MII_ERROR (1<<19)
441 #define RX_DRIBBLING (1<<20)
442 #define RX_CRC_ERROR (1<<21)
443 #define RX_VLAN1 (1<<22)
444 #define RX_VLAN2 (1<<23)
445 #define RX_LEN_ERROR (1<<24)
446 #define RX_CNTRL_FRAME (1<<25)
447 #define RX_U_CNTRL_FRAME (1<<26)
448 #define RX_MCAST_FRAME (1<<27)
449 #define RX_BCAST_FRAME (1<<28)
450 #define RX_FILTER_FAIL (1<<29)
451 #define RX_PACKET_FILTER (1<<30)
452 #define RX_MISSED_FRAME (1<<31)
453
454 #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
455 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
456 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
457 #define MAC_RX_BUFF0_ADDR 0x4
458 #define RX_DMA_ENABLE (1<<0)
459 #define RX_T_DONE (1<<1)
460 #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
461 #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
462 #define MAC_RX_BUFF1_STATUS 0x10
463 #define MAC_RX_BUFF1_ADDR 0x14
464 #define MAC_RX_BUFF2_STATUS 0x20
465 #define MAC_RX_BUFF2_ADDR 0x24
466 #define MAC_RX_BUFF3_STATUS 0x30
467 #define MAC_RX_BUFF3_ADDR 0x34
468
469
470 /* UARTS 0-3 */
471 #define UART0_ADDR 0x11100000
472 #define UART1_ADDR 0x11200000
473 #define UART2_ADDR 0x11300000
474 #define UART3_ADDR 0x11400000
475
476 #define UART_RX 0 /* Receive buffer */
477 #define UART_TX 4 /* Transmit buffer */
478 #define UART_IER 8 /* Interrupt Enable Register */
479 #define UART_IIR 0xC /* Interrupt ID Register */
480 #define UART_FCR 0x10 /* FIFO Control Register */
481 #define UART_LCR 0x14 /* Line Control Register */
482 #define UART_MCR 0x18 /* Modem Control Register */
483 #define UART_LSR 0x1C /* Line Status Register */
484 #define UART_MSR 0x20 /* Modem Status Register */
485 #define UART_CLK 0x28 /* Baud Rat4e Clock Divider */
486 #define UART_MOD_CNTRL 0x100 /* Module Control */
487
488 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
489 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
490 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
491 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
492 #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
493 #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
494 #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
495 #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
496 #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
497 #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
498 #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
499 #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
500 #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
501
502 /*
503 * These are the definitions for the Line Control Register
504 */
505 #define UART_LCR_SBC 0x40 /* Set break control */
506 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */
507 #define UART_LCR_EPAR 0x10 /* Even parity select */
508 #define UART_LCR_PARITY 0x08 /* Parity Enable */
509 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
510 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
511 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
512 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
513 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
514
515 /*
516 * These are the definitions for the Line Status Register
517 */
518 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
519 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
520 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
521 #define UART_LSR_FE 0x08 /* Frame error indicator */
522 #define UART_LSR_PE 0x04 /* Parity error indicator */
523 #define UART_LSR_OE 0x02 /* Overrun error indicator */
524 #define UART_LSR_DR 0x01 /* Receiver data ready */
525
526 /*
527 * These are the definitions for the Interrupt Identification Register
528 */
529 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
530 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
531 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
532 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
533 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
534 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
535
536 /*
537 * These are the definitions for the Interrupt Enable Register
538 */
539 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
540 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
541 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
542 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
543
544 /*
545 * These are the definitions for the Modem Control Register
546 */
547 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
548 #define UART_MCR_OUT2 0x08 /* Out2 complement */
549 #define UART_MCR_OUT1 0x04 /* Out1 complement */
550 #define UART_MCR_RTS 0x02 /* RTS complement */
551 #define UART_MCR_DTR 0x01 /* DTR complement */
552
553 /*
554 * These are the definitions for the Modem Status Register
555 */
556 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
557 #define UART_MSR_RI 0x40 /* Ring Indicator */
558 #define UART_MSR_DSR 0x20 /* Data Set Ready */
559 #define UART_MSR_CTS 0x10 /* Clear to Send */
560 #define UART_MSR_DDCD 0x08 /* Delta DCD */
561 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
562 #define UART_MSR_DDSR 0x02 /* Delta DSR */
563 #define UART_MSR_DCTS 0x01 /* Delta CTS */
564 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
565
566
567
568 /* SSIO */
569 #define SSI0_STATUS 0x11600000
570 #define SSI0_INT 0x11600004
571 #define SSI0_INT_ENABLE 0x11600008
572 #define SSI0_CONFIG 0x11600020
573 #define SSI0_ADATA 0x11600024
574 #define SSI0_CLKDIV 0x11600028
575 #define SSI0_CONTROL 0x11600100
576
577 /* SSI1 */
578 #define SSI1_STATUS 0x11680000
579 #define SSI1_INT 0x11680004
580 #define SSI1_INT_ENABLE 0x11680008
581 #define SSI1_CONFIG 0x11680020
582 #define SSI1_ADATA 0x11680024
583 #define SSI1_CLKDIV 0x11680028
584 #define SSI1_CONTROL 0x11680100
585
586 /* IrDA Controller */
587 #define IR_RING_PTR_STATUS 0x11500000
588 #define IR_RING_BASE_ADDR_H 0x11500004
589 #define IR_RING_BASE_ADDR_L 0x11500008
590 #define IR_RING_SIZE 0x1150000C
591 #define IR_RING_PROMPT 0x11500010
592 #define IR_RING_ADDR_CMPR 0x11500014
593 #define IR_CONFIG_1 0x11500020
594 #define IR_SIR_FLAGS 0x11500024
595 #define IR_ENABLE 0x11500028
596 #define IR_READ_PHY_CONFIG 0x1150002C
597 #define IR_WRITE_PHY_CONFIG 0x11500030
598 #define IR_MAX_PKT_LEN 0x11500034
599 #define IR_RX_BYTE_CNT 0x11500038
600 #define IR_CONFIG_2 0x1150003C
601 #define IR_INTERFACE_CONFIG 0x11500040
602
603 /* GPIO */
604 #define TSTATE_STATE_READ 0x11900100
605 #define TSTATE_STATE_SET 0x11900100
606 #define OUTPUT_STATE_READ 0x11900108
607 #define OUTPUT_STATE_SET 0x11900108
608 #define OUTPUT_STATE_CLEAR 0x1190010C
609 #define PIN_STATE 0x11900110
610
611 /* Power Management */
612 #define PM_SCRATCH_0 0x11900018
613 #define PM_SCRATCH_1 0x1190001C
614 #define PM_WAKEUP_SOURCE_MASK 0x11900034
615 #define PM_ENDIANESS 0x11900038
616 #define PM_POWERUP_CONTROL 0x1190003C
617 #define PM_WAKEUP_CAUSE 0x1190005C
618 #define PM_SLEEP_POWER 0x11900078
619 #define PM_SLEEP 0x1190007C
620
621 /* Clock Controller */
622 #define FQ_CNTRL_1 0x11900020
623 #define FQ_CNTRL_2 0x11900024
624 #define CLOCK_SOURCE_CNTRL 0x11900028
625 #define CPU_PLL_CNTRL 0x11900060
626 #define AUX_PLL_CNTRL 0x11900064
627
628 /* AC97 Controller */
629 #define AC97_CONFIG 0x10000000
630 #define AC97_STATUS 0x10000004
631 #define AC97_DATA 0x10000008
632 #define AC97_CMD 0x1000000C
633 #define AC97_CNTRL 0x10000010
634
635 #endif
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