au1000.txt

linux 操作系统下的驱动程序开发例子

au1000.hFile: /usr/src/linux/include/asm-mips/au1000.h
1     /*
2      *
3      * BRIEF MODULE DESCRIPTION
4      *	Include file for Alchemy Semiconductor's Au1000 CPU.
5      *
6      * Copyright 2000 MontaVista Software Inc.
7      * Author: MontaVista Software, Inc.
8      *         	[e-mail] or [e-mail]
9      *
10      *  This program is free software; you can redistribute  it and/or modify it
11      *  under  the terms of  the GNU General  Public License as published by the
12      *  Free Software Foundation;  either version 2 of the  License, or (at your
13      *  option) any later version.
14      *
15      *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
16      *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
17      *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
18      *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
19      *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20      *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
21      *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22      *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
23      *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24      *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25      *
26      *  You should have received a copy of the  GNU General Public License along
27      *  with this program; if not, write  to the Free Software Foundation, Inc.,
28      *  675 Mass Ave, Cambridge, MA 02139, USA.
29      */
30     
31     #ifndef _AU1000_H_
32     #define _AU1000_H_
33     
34     /* SDRAM Controller */
35     #define CS_MODE_0                0x14000000
36     #define CS_MODE_1                0x14000004
37     #define CS_MODE_2                0x14000008
38     
39     #define CS_CONFIG_0              0x1400000C
40     #define CS_CONFIG_1              0x14000010
41     #define CS_CONFIG_2              0x14000014
42     
43     #define REFRESH_CONFIG           0x14000018
44     #define PRECHARGE_CMD            0x1400001C
45     #define AUTO_REFRESH_CMD         0x14000020
46     
47     #define WRITE_EXTERN_0           0x14000024
48     #define WRITE_EXTERN_1           0x14000028
49     #define WRITE_EXTERN_2           0x1400002C
50     
51     #define SDRAM_SLEEP              0x14000030
52     #define TOGGLE_CKE               0x14000034
53     
54     /* Static Bus Controller */
55     #define STATIC_CONFIG_0          0x14001000
56     #define STATIC_TIMING_0          0x14001004
57     #define STATIC_ADDRESS_0         0x14001008
58     
59     #define STATIC_CONFIG_1          0x14001010
60     #define STATIC_TIMING_1          0x14001014
61     #define STATIC_ADDRESS_1         0x14001018
62     
63     #define STATIC_CONFIG_2          0x14001020
64     #define STATIC_TIMING_2          0x14001024
65     #define STATIC_ADDRESS_2         0x14001028
66     
67     #define STATIC_CONFIG_3          0x14001030
68     #define STATIC_TIMING_3          0x14001034
69     #define STATIC_ADDRESS_3         0x14001038
70     
71     /* DMA Controller 0 */
72     #define DMA0_MODE_SET            0x14002000
73     #define DMA0_MODE_CLEAR          0x14002004
74     #define DMA0_PERIPHERAL_ADDR     0x14002008
75     #define DMA0_BUFFER0_START       0x1400200C
76     #define DMA0_BUFFER0_COUNT       0x14002010
77     #define DMA0_BUFFER1_START       0x14002014
78     #define DMA0_BUFFER1_COUNT       0x14002018
79     
80     /* DMA Controller 1 */
81     #define DMA1_MODE_SET            0x14002100
82     #define DMA1_MODE_CLEAR          0x14002104
83     #define DMA1_PERIPHERAL_ADDR     0x14002108
84     #define DMA1_BUFFER0_START       0x1400210C
85     #define DMA1_BUFFER0_COUNT       0x14002110
86     #define DMA1_BUFFER1_START       0x14002114
87     #define DMA1_BUFFER1_COUNT       0x14002118
88     
89     /* DMA Controller 2 */
90     #define DMA2_MODE_SET            0x14002200
91     #define DMA2_MODE_CLEAR          0x14002204
92     #define DMA2_PERIPHERAL_ADDR     0x14002208
93     #define DMA2_BUFFER0_START       0x1400220C
94     #define DMA2_BUFFER0_COUNT       0x14002210
95     #define DMA2_BUFFER1_START       0x14002214
96     #define DMA2_BUFFER1_COUNT       0x14002218
97     
98     /* DMA Controller 3 */
99     #define DMA3_MODE_SET            0x14002300
100     #define DMA3_MODE_CLEAR          0x14002304
101     #define DMA3_PERIPHERAL_ADDR     0x14002308
102     #define DMA3_BUFFER0_START       0x1400230C
103     #define DMA3_BUFFER0_COUNT       0x14002310
104     #define DMA3_BUFFER1_START       0x14002314
105     #define DMA3_BUFFER1_COUNT       0x14002318
106     
107     /* DMA Controller 4 */
108     #define DMA4_MODE_SET            0x14002400
109     #define DMA4_MODE_CLEAR          0x14002404
110     #define DMA4_PERIPHERAL_ADDR     0x14002408
111     #define DMA4_BUFFER0_START       0x1400240C
112     #define DMA4_BUFFER0_COUNT       0x14002410
113     #define DMA4_BUFFER1_START       0x14002414
114     #define DMA4_BUFFER1_COUNT       0x14002418
115     
116     /* DMA Controller 5 */
117     #define DMA5_MODE_SET            0x14002500
118     #define DMA5_MODE_CLEAR          0x14002504
119     #define DMA5_PERIPHERAL_ADDR     0x14002508
120     #define DMA5_BUFFER0_START       0x1400250C
121     #define DMA5_BUFFER0_COUNT       0x14002510
122     #define DMA5_BUFFER1_START       0x14002514
123     #define DMA5_BUFFER1_COUNT       0x14002518
124     
125     /* DMA Controller 6 */
126     #define DMA6_MODE_SET            0x14002600
127     #define DMA6_MODE_CLEAR          0x14002604
128     #define DMA6_PERIPHERAL_ADDR     0x14002608
129     #define DMA6_BUFFER0_START       0x1400260C
130     #define DMA6_BUFFER0_COUNT       0x14002610
131     #define DMA6_BUFFER1_START       0x14002614
132     #define DMA6_BUFFER1_COUNT       0x14002618
133     
134     /* DMA Controller 7 */
135     #define DMA7_MODE_SET            0x14002700
136     #define DMA7_MODE_CLEAR          0x14002704
137     #define DMA7_PERIPHERAL_ADDR     0x14002708
138     #define DMA7_BUFFER0_START       0x1400270C
139     #define DMA7_BUFFER0_COUNT       0x14002710
140     #define DMA7_BUFFER1_START       0x14002714
141     #define DMA7_BUFFER1_COUNT       0x14002718
142     
143     /* Interrupt Controller 0 */
144     #define INTC0_CONFIG0_READ        0x10400040
145     #define INTC0_CONFIG0_SET         0x10400040
146     #define INTC0_CONFIG0_CLEAR       0x10400044
147     
148     #define INTC0_CONFIG1_READ        0x10400048
149     #define INTC0_CONFIG1_SET         0x10400048
150     #define INTC0_CONFIG1_CLEAR       0x1040004C
151     
152     #define INTC0_CONFIG2_READ        0x10400050
153     #define INTC0_CONFIG2_SET         0x10400050
154     #define INTC0_CONFIG2_CLEAR       0x10400054
155     
156     #define INTC0_REQ0_INT            0x10400054
157     #define INTC0_SOURCE_READ         0x10400058
158     #define INTC0_SOURCE_SET          0x10400058
159     #define INTC0_SOURCE_CLEAR        0x1040005C
160     #define INTC0_REQ1_INT            0x1040005C
161     
162     #define INTC0_ASSIGN_REQ_READ     0x10400060
163     #define INTC0_ASSIGN_REQ_SET      0x10400060
164     #define INTC0_ASSIGN_REQ_CLEAR    0x10400064
165     
166     #define INTC0_WAKEUP_READ         0x10400068
167     #define INTC0_WAKEUP_SET          0x10400068
168     #define INTC0_WAKEUP_CLEAR        0x1040006C
169     
170     #define INTC0_MASK_READ           0x10400070
171     #define INTC0_MASK_SET            0x10400070
172     #define INTC0_MASK_CLEAR          0x10400074
173     
174     #define INTC0_R_EDGE_DETECT       0x10400078
175     #define INTC0_R_EDGE_DETECT_CLEAR 0x10400078
176     #define INTC0_F_EDGE_DETECT_CLEAR 0x1040007C
177     
178     #define INTC0_TEST_BIT            0x10400080
179     
180     /* Interrupt Controller 1 */
181     #define INTC1_CONFIG0_READ        0x11800040
182     #define INTC1_CONFIG0_SET         0x11800040
183     #define INTC1_CONFIG0_CLEAR       0x11800044
184     
185     #define INTC1_CONFIG1_READ        0x11800048
186     #define INTC1_CONFIG1_SET         0x11800048
187     #define INTC1_CONFIG1_CLEAR       0x1180004C
188     
189     #define INTC1_CONFIG2_READ        0x11800050
190     #define INTC1_CONFIG2_SET         0x11800050
191     #define INTC1_CONFIG2_CLEAR       0x11800054
192     
193     #define INTC1_REQ0_INT            0x11800054
194     #define INTC1_SOURCE_READ         0x11800058
195     #define INTC1_SOURCE_SET          0x11800058
196     #define INTC1_SOURCE_CLEAR        0x1180005C
197     #define INTC1_REQ1_INT            0x1180005C
198     
199     #define INTC1_ASSIGN_REQ_READ     0x11800060
200     #define INTC1_ASSIGN_REQ_SET      0x11800060
201     #define INTC1_ASSIGN_REQ_CLEAR    0x11800064
202     
203     #define INTC1_WAKEUP_READ         0x11800068
204     #define INTC1_WAKEUP_SET          0x11800068
205     #define INTC1_WAKEUP_CLEAR        0x1180006C
206     
207     #define INTC1_MASK_READ           0x11800070
208     #define INTC1_MASK_SET            0x11800070
209     #define INTC1_MASK_CLEAR          0x11800074
210     
211     #define INTC1_R_EDGE_DETECT       0x11800078
212     #define INTC1_R_EDGE_DETECT_CLEAR 0x11800078
213     #define INTC1_F_EDGE_DETECT_CLEAR 0x1180007C
214     
215     #define INTC1_TEST_BIT            0x11800080
216     
217     /* Interrupt Configuration Modes */
218     #define INTC_INT_DISABLED                0
219     #define INTC_INT_RISE_EDGE             0x1
220     #define INTC_INT_FALL_EDGE             0x2
221     #define INTC_INT_RISE_AND_FALL_EDGE    0x3
222     #define INTC_INT_HIGH_LEVEL            0x5
223     #define INTC_INT_LOW_LEVEL             0x6
224     #define INTC_INT_HIGH_AND_LOW_LEVEL    0x7
225     
226     /* Interrupt Numbers */
227     #define AU1000_UART0_INT          0
228     #define AU1000_UART1_INT          1
229     #define AU1000_UART2_INT          2
230     #define AU1000_UART3_INT          3
231     #define AU1000_SSI0_INT           4
232     #define AU1000_SSI1_INT           5
233     #define AU1000_DMA0_INT           6
234     #define AU1000_DMA1_INT           7
235     #define AU1000_DMA2_INT           8
236     #define AU1000_DMA3_INT           9
237     #define AU1000_DMA4_INT           10
238     #define AU1000_DMA5_INT           11
239     #define AU1000_DMA6_INT           12
240     #define AU1000_DMA7_INT           13
241     #define AU1000_PC0_INT            14
242     #define AU1000_PC0_MATCH0_INT     15
243     #define AU1000_PC0_MATCH1_INT     16
244     #define AU1000_PC0_MATCH2_INT     17
245     #define AU1000_PC1_INT            18
246     #define AU1000_PC1_MATCH0_INT     19
247     #define AU1000_PC1_MATCH1_INT     20
248     #define AU1000_PC1_MATCH2_INT     21
249     #define AU1000_IRDA_TX_INT        22
250     #define AU1000_IRDA_RX_INT        23
251     #define AU1000_USB_DEV_REQ_INT    24
252     #define AU1000_USB_DEV_SUS_INT    25
253     #define AU1000_USB_HOST_INT       26
254     #define AU1000_ACSYNC_INT         27
255     #define AU1000_MAC0_DMA_INT       28
256     #define AU1000_MAC1_DMA_INT       29
257     #define AU1000_ETH0_IRQ           AU1000_MAC0_DMA_INT
258     #define AU1000_ETH1_IRQ           AU1000_MAC1_DMA_INT
259     #define AU1000_I2S_UO_INT         30
260     #define AU1000_AC97_INT           31
261     #define AU1000_LAST_INTC0_INT     AU1000_AC97_INT
262     #define AU1000_GPIO_0             32
263     #define AU1000_GPIO_1             33
264     #define AU1000_GPIO_2             34
265     #define AU1000_GPIO_3             35
266     #define AU1000_GPIO_4             36
267     #define AU1000_GPIO_5             37
268     #define AU1000_GPIO_6             38
269     #define AU1000_GPIO_7             39
270     #define AU1000_GPIO_8             40
271     #define AU1000_GPIO_9             41
272     #define AU1000_GPIO_10            42
273     #define AU1000_GPIO_11            43
274     #define AU1000_GPIO_12            44
275     #define AU1000_GPIO_13            45
276     #define AU1000_GPIO_14            46
277     #define AU1000_GPIO_15            47
278     #define AU1000_GPIO_16            48
279     #define AU1000_GPIO_17            49
280     #define AU1000_GPIO_18            50
281     #define AU1000_GPIO_19            51
282     #define AU1000_GPIO_20            52
283     #define AU1000_GPIO_21            53
284     #define AU1000_GPIO_22            54
285     #define AU1000_GPIO_23            55
286     #define AU1000_GPIO_24            56
287     #define AU1000_GPIO_25            57
288     #define AU1000_GPIO_26            58
289     #define AU1000_GPIO_27            59
290     #define AU1000_GPIO_28            60
291     #define AU1000_GPIO_29            61
292     #define AU1000_GPIO_30            62
293     #define AU1000_GPIO_31            63
294     
295     /* Programmable Counters 0 and 1 */
296     #define PC_BASE                   0x11900000
297     #define PC_COUNTER_CNTRL          (PC_BASE + 0x14)
298       #define PC_CNTRL_E1S            (1<<23)
299       #define PC_CNTRL_T1S            (1<<20)
300       #define PC_CNTRL_M21            (1<<19)
301       #define PC_CNTRL_M11            (1<<18)
302       #define PC_CNTRL_M01            (1<<17)
303       #define PC_CNTRL_C1S            (1<<16)
304       #define PC_CNTRL_BP             (1<<14)
305       #define PC_CNTRL_EN1            (1<<13)
306       #define PC_CNTRL_BT1            (1<<12)
307       #define PC_CNTRL_EN0            (1<<11)
308       #define PC_CNTRL_BT0            (1<<10)
309       #define PC_CNTRL_E0             (1<<8)
310       #define PC_CNTRL_E0S            (1<<7)
311       #define PC_CNTRL_32S            (1<<5)
312       #define PC_CNTRL_T0S            (1<<4)
313       #define PC_CNTRL_M20            (1<<3)
314       #define PC_CNTRL_M10            (1<<2)
315       #define PC_CNTRL_M00            (1<<1)
316       #define PC_CNTRL_C0S            (1<<0)
317     
318     /* Programmable Counter 0 Registers */