fgsshift4.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 19 行

ARCHITECTURE fgshift4x OF fgshift4 IS
  COMPONENT dffx 
    PORT(d,cp:IN STD_LOGIC;
         q:OUT STD_LOGIC);
  END COMPONENT;
  SIGNAL temp:STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
  g1:FOR i IN  4 DOWNTO 1  GENERATE
       IF(i=3) GENERATE
          dffn:dffx PORT MAP(din,clk,temp(i-1));
       END GENERATE;
       IF(i=0) GENERATE
          dffn:dffx PORT MAP(temp(i),clk,dout);
       END GENERATE;
       IF(i/=3) AND (i/=0) GENERATE 
          dffn: dffx PORT MAP (temp(i),clk,temp(i-1));
       END GENERATE;
END fgshift4x;