coder42.vhd

《CPLD_FPGA设计及应用》课件与实例

library ieee;
use ieee.std_logic_1164.all;
entity coder42 is 
  port(inx:in std_logic_vector(3 downto 0);
       y:out std_logic_vector(1 downto 0));
end coder42;
architecture bevcoder of coder42 is
begin
  process(inx)
  begin
    if (inx(3)='1')  then
      y<="11";
    elsif  (inx(2)='1')  then
      y<="10"; 
    elsif  (inx(1)='1')  then
      y<="01"; 
    else
      y<="00";
    end if;
  end process;
end bevcoder;