f1shift4.vhd

《CPLD_FPGA设计及应用》课件与实例

library ieee;
use ieee.std_logic_1164.all;
entity flshift4 is
  port(din,clk:in std_logic;
       dout:out std_logic);
end flshift4;
architecture bevsft4 of flshift8 is
  signal temp:std_logic_vector(3 downto 0);
begin
  process(clk,temp)
  begin
     if (clk'event and clk='1')  then
     temp(3)<=din;
       for i in 0 to 2 loop
         temp(i)<=temp(i+1);
       end loop;
     end if;
     dout<=temp(0);
  end process;
end  bevsft4;