exparaevala.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 18 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY exparaevala IS
  PORT(a,b:IN STD_LOGIC;
       f1,f2:OUT STD_LOGIC);
END exparaevala;
ARCHITECTURE exevala OF exparaevala IS
BEGIN
  p1:PROCESS(a,b)
     BEGIN 
       f1<=a AND b;
     END PROCESS;
  p2:PROCESS(a,b)
     BEGIN
      f2<=a nor b;
     END PROCESS;
END exevala;