csif2.vhd

《CPLD_FPGA设计及应用》课件与实例

library ieee;
use ieee.std_logic_1164.all;
entity csif2 is
  port(a,b:in std_logic;
       y:out std_logic);
end csif2;
architecture csif of csif2 is
begin
  process(a)
  begin
    if (a='1') then
       y<=a;
    else
       y<=b;
    end if;
  end process;
end csif;