bkfa.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 33 行

library ieee;
use ieee.std_logic_1164.all;
entity  bkfa is
  port(a,b,cin:in std_logic;
       co,sum:out std_logic);
end bkfa;
architecture fadder of bkfa is
begin
  fa:block
       port(tempa,tempb,tempcin:in std_logic;
            tempco,tempsum:out std_logic);
       port map (a,b,cin,co,sum);
       signal temp1,temp2:std_logic;
     begin
       p1:process(tempa,tempb)
          begin
            temp1<=tempa xor tempb;
          end process p1;
       p2:process(temp1,tempb)
          begin
            temp2<=temp1 and tempb;
          end process p2;
       p3:process(temp1,tempcin)
          begin
            tempsum<=temp1 xor tempcin;
          end process p3;
       p4:process(tempa,tempb,tempcin,temp1)
          begin
            tempco<=(tempcin and temp1) or (tempa and tempb);
          end process p4;
end block fa;
end fadder;