paraeval.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 12 行

library ieee;
use ieee.std_logic_1164.all;
entity paraeval is
  port(a,b:in std_logic;
       f1,f2:out std_logic);
end paraeval;
architecture exeval of paraeval is
begin
    f1<=a and b;
    f2<=a nor b;
end exeval;